劉致為臺灣大學：電子工程學研究所詹孫戎Jan, Sun-RongSun-RongJan2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57383以往電晶體尺寸縮小的速度可以如Moore定律預期的步伐進行下去，但是現今尺寸縮小的速度越趨緩慢，原因在於尺寸縮小即將到達其物理極限。傳統的尺寸縮小技術已經不敷使用，為了能繼續增進電晶體的速度與操作效能，勢必要發展出創新的改善方法。 施加機械應變於電晶體可以增強電流，增進電晶體效能。本篇論文探討了施加機械應於各種電晶體後的變化，有N型及P型金氧半場效體，BJT，HBT等。變機械應變可以於封裝過程中加入，因此又稱為封裝應變。封裝應變易於與現行的半導體技術整合。 SOI（Silicon On Insulator）也是目前研究發展的創新技術之ㄧ，SOI以晶圓鍵合為基礎。在晶圓鍵合方面，設計了快熱製程機台的多平面反射體，可以幫助晶圓在快熱製程中受熱更均勻，也設計了可以幫助四吋晶圓鍵合的機台。 另一研究發展的技術為製程應變，可以經由半導體製程產生應變，製程應變可以是單軸的或是部份區域的，故又稱為局部應變。現今常用的製程應變為，於N型金氧半場效體上方覆誘@層強硬力氮化物，藉此對通道產生張應變。應用了ANSYS與ISE等模擬軟體，模擬討論製程應變的影響。In the past, the speed of shrinking the dimensions of the transistors can proceed with Moore’s law. However, the speed of shrinking dimensions becomes slower and slower nowadays. This is because that the dimensions shrinking will face the physical limitation. The traditional technique of shrinking dimensions is not enough. In order to continue improving the transistor speed and performance, it is essential to create new techniques. Applying mechanical strain to transistor can enhances drive current and improves performance. In this thesis, we discuss the variation after applying strain to various semiconductors, such as NMOS, PMOS, BJT, HBT, etc… Mechanical strain can be applied to the semiconductors in the package process. Therefore, mechanical strain is also called package strain. Package strain is easy to integrate with present semiconductor techniques. SOI（Silicon On Insulator）is one of the popular study of innovation techniques. SOI is on the base of wafer bonding. Relative to wafer bonding, we designed a multi-plane reflector applied in the RTP (Rapid Thermal Process). It can help wafer absorb energy more uniformly in RTP. We designed a device to help 4” wafer bonding. Another popular technique is process strain. The strain can be produced in the semiconductor process. The process strain is uni-axial or local, so it is called local strain. The usual method to induce process strain is to glow a highly strained nitride cap layer beneath the NMOS. This way, there is tensile strain induced in the channel. We use some simulation software like ANSYS and ISE to simulate and discuss the effect of strain.Chapter 1 Introduction 1 Chapter 2 Mechanically Strained-MOS 3 2.1 Mechanically Strained-Silicon NMOSFETs 3 2.1.1 Introduction 4 2.1.2 Experiment 4 2.1.3 Results and Discussion 7 2.1.4 Conclusion 11 2.2 Comprehensive study of mechanically strained-Si PMOSFETs 12 2.2.1 Introduction 12 2.2.2 Experiment 13 2.2.3 Results and Discussion 15 2.2.4 Conclusion 20 Chapter 3 Mechanically strained Si/SiGe HBTs 25 3.1 Introduction 25 3.2 Experiment 26 3.3 Results and Discussion 27 3.4 Conclusion 34 Chapter 4 Reflector of RTP and Wafer Bonding 37 4.1 Reflector of RTP 37 4.1.1 Modeling 37 4.1.2 Multi-plane Reflector 40 4.1.3 Simulation 41 4.2 Wafer Bonding 43 4.2.1 Wafer Bonding device 44 4.2.2 Experiment 47 4.3 Summary 49 Chapter 5 Process (Local) Strained-Silicon Simulation 51 5.1 Strained-Si 52 5.2 ANSYS Simulation 55 5.3 ISE simulation 58 5.3.1 Thickness 58 5.3.2 Spacer 59 5.3.3 Shrink 62 5.3.4 Summary 65 Chapter 6 Summary and Future work 682099225 bytesapplication/pdfen-US應變矽技術晶圓鍵合wafer bondingstrained-Si techniquesthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57383/1/ntu-93-R91943100-1.pdf