Chang, C.-K.C.-K.ChangTsai, Y.-K.Y.-K.TsaiCheng, K.-H.K.-H.ChengLIANG-HUNG LU2020-06-112020-06-112017https://scholars.lib.ntu.edu.tw/handle/123456789/498168https://www.scopus.com/inward/record.uri?eid=2-s2.0-85034432292&doi=10.1109%2fNEWCAS.2017.8010145&partnerID=40&md5=bc5d639972db7821e9485b3f0f63c8a5An energy efficient delta-sigma time-to-digital converter (TDC) is presented in this paper. Compared with conventional circuit techniques, non-ideal effects associated with switching noise and transistor leakage can be generally prevented due to the use of a gated-free ring oscillator and leakage-suppression switches in the circuit implementation. The proposed TDC is fabricated in 90-nm CMOS, consuming a current of 5 μA from a 0.3-V supply. With first-order shaping of the quantization noise, the circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50-kHz signal bandwidth. © 2017 IEEE.Low power; Low voltage; Noise shaping; Oversampling; Time-domain; Time-to-digital converter (TDC)[SDGs]SDG7Energy efficiency; Oscillators (electronic); Quantization (signal); Signal processing; Time domain analysis; Low Power; Low voltages; Noise-shaping; Over sampling; Time domain; Time to digital converters; Frequency convertersconference paper10.1109/NEWCAS.2017.80101452-s2.0-85034432292