呂學士臺灣大學:電機工程學研究所周宗漢Chou, Zong-HanZong-HanChou2010-07-012018-07-062010-07-012018-07-062009U0001-1708200922575900http://ntur.lib.ntu.edu.tw//handle/246246/188066隨著近半導體技術的發展，很多電子產品都可以整合進CMOS 電路。本論文使用台積電0.35微米 2P4M CMOS技術實現與適用於BS EN50065-1 classic規範的電力線通訊收發機。本論文包含兩顆晶片，第一顆為一個具有56種不同電壓增益的自動增益放大器，令一顆則是以FSK為解調方式的電力線通訊收發機。前饋回授的自動增益放大器包含可調整增益的電壓增益放大器、峰值檢測器、類比數位轉換器還有控制單元，晶片面積為1.41mm × 1.64mm，功率消耗為2.12mW。另外符合BS EN50065-1 class C的電力線通訊收發機包含FSK訊號產生器、可調整增益的電壓增益放大器、低通濾波器、峰值檢測器和遲滯比較器，晶片面積為1.68mm × 1.929mm，功率消耗為43.26mW。With the development of semiconductor technology, many electronic products 1re integrated with CMOS circuit. This thesis uses TSMC 0.35 micron 2P4M CMOS technology to implement a transceiver compatible with BS EN50065-1 class C standard. This work included two chips. One is an automatic gain control amplifier with fifty-six voltage gains, and the other is a power line communication transceiver with FSK modulation. he feed-forward automatic gain control amplifier is composed of programmable gain amplifier, peak detector, analog-to-digital converter, and control unit. The die area is 1.41mm ? 1.64mm, and the power consumption is 2.12mW. On the other hand, the power line communication transceiver which is compatible with BS EN50065-1 class C standard included FSK signal generator, programmable gain amplifier, low pass filter, peak detector, and hysteresis comparator with total die area of 1.68mm ? 1.929mm, and the power consumption is 43.26mW..List of contentshinese Abstract IIInglish Abstract Vist of Contents VIIndex of Figures XIIIndex of Tables XVIIhapter1 1.1 Motivation 1.2 Thesis Overview 3hapter2 5.1 Motivation 5.2 Power line noise interference 6.2.1 High noise 6.2.2 High attenuation 7.2.3 Signal distortion 9.3 Power line communication specification and standard 9.3.1 Power line communication specification 10.3.2 Power line communication standard 11.4 Power line communication modulation 12.4.1 ASK (Amplitude Shift Keying) 12.4.2 FSK (Frequency Shift Keying) 13.4.3 PSK (Phase Shift Keying) 13.5 Summary 14hapter3 15.1 Introduction 15.2 System Architecture and Specifications [12] 16.3 Implementation of proposed automatic-gain control amplifier 17.3.1 Programmable gain amplifier (PGA) 17.3.2 Rail-to-Rail Operational Amplifier 20.3.3 Peak detector 22.3.4 Analog-to-digital converter (ADC) [18] 24.3.5 Control unit 25.3 Layout 25hapter 4 27.1 Introduction 27.2 System block design of low speed PLC transceiver 28.3 Implementation of proposed power line communication transceiver 29.3.1 FSK signal generator 29.3.2 Programmable gain amplifier 31.3.3 Operational amplifier design 31.3.4 Filter implementation 35.3.4.1 Magnitude characteristics 35.3.4.2 Conventional filter types 36.3.4.3 Circuit implementation 38.3.4.3.1 Cascade design 38.3.4.3.2 Biquad implementation 38.3.5 Peak detector 44.3.6 Hysteresis comparator 45.3 Layout 48hapter5 49.1 Measurement results of automatic gain control 49.1.1 AC response measurement result of programmable gain amplifier 50.1.2 Measurement results of automatic gain control 51.1.1 AC response measurement result of the 13th-order low pass filter 56.1.2 Measurement results of the power line communication 58hapter6 65eferences 67ppendix A 711540279 bytesapplication/pdfen-US電力線通訊自動增益放大器power line communicationAGCthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188066/1/ntu-98-J96921037-1.pdf