M.-L. FanC.-Y. HsiehP. SuC.-T. ChuangVITA PI-HO HU2020-10-072020-10-07201100189383https://scholars.lib.ntu.edu.tw/handle/123456789/516609https://www.scopus.com/inward/record.uri?eid=2-s2.0-79952024489&doi=10.1109%2fTED.2010.2099661&partnerID=40&md5=a4c3facbf5804b89cdeee5d34187ea50This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading read static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of write SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-κ metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO2 and SiO2/HfO2) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM. © 2011 IEEE.FinFET; negative bias temperature instability (NBTI); positive bias temperature instability (PBTI); static random access memory (SRAM); surface orientation; variabilityFinFET; Negative bias temperature instability; Positive bias temperature instabilities; static random access memory (SRAM); surface orientation; variability; Cell membranes; Degradation; Field effect transistors; Fins (heat exchange); Gate dielectrics; Gates (transistor); Hafnium compounds; Integrated circuits; MESFET devices; Negative temperature coefficient; Optimization; Silicon compounds; Thermodynamic stability; Static random access storagejournal article10.1109/ted.2010.20996612-s2.0-79952024489