顧孟愷臺灣大學：資訊工程學研究所林宜德Lin, Yi-derYi-derLin2007-11-262018-07-052007-11-262018-07-052006http://ntur.lib.ntu.edu.tw//handle/246246/54125One of the difficult problems of hardware/software codesign flow is hardware/software partitioning which decides each component of the system to be implemented as hardware or software. The hw/sw (hardware/software) partitioning determines the performance and hardware resource used of the partitioned system. Hw/sw exploration helps us make the decision. It explores pros and cons of all possible hw/sw partitioned systems. We present a system model and hw/sw communication optimization to explore execution time of a partitioned system more precisely. At the same time, they can improve traditional codesign flow. The system model can reduce hw/sw integration and implementation effort and hw/sw communication optimization can reduce hw/sw communication overhead. Low-Density Parity Check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. Therefore, we take LDPC decoder as the case study. After successfully applying our method to LDPC decoder, we can find out different hw/sw partitioned LDPC decoders to satisfy different needs according to the hw/sw exploration results. Finally, we did implement four kinds of hw/sw partitioned LDPC decoders. By analyzing the experiments results, there is a tradeoff between performance, hardware resource and flexibility.ACKNOWLEDGEMENTS ii ABSTRACT iii Table of Contents iv Table of Figures vi List of Tables viii Chapter 1 Introduction 1 1.1 Typical HW/SW Codesign Flow 1 1.2 HW/SW Exploration 3 1.3 LDPC Decoder 4 1.3.1 Tanner Graph and Parity Check Matrix 4 1.3.2 Iterative and Two Phases Decoding Algorithm 6 1.4 Thesis Organization 6 Chapter 2 Related Work 8 2.1 System Modeling 8 2.2 Hardware/Software Partitioning 12 Chapter 3 Hardware/Software Exploration 14 3.1 System Modeling 14 3.2 HW/SW Communication Optimization 15 3.3 HW/SW Exploration 17 Chapter 4 Implementation of LDPC Decoder 20 4.1 Target Platform and Development Environment 20 4.2 HW/SW Exploration of LDPC Decoder 24 4.2.1 System Specification 24 4.2.2 System Modeling 24 4.2.3 HW/SW Communication Optimization 35 4.2.4 HW/SW Exploration 37 4.3 Experimental Results 43 Chapter 5 Conclusion and Future Work 46 5.1 Conclusion 46 5.2 Future Work 47 Reference 48en-US軟硬體分割低密度奇偶校驗碼hardware/software partitioninghardware/software codesignhardware/software explorationhw/sw explorationhw/sw partitioninghw/sw codesignldpcthesis