李致毅臺灣大學：電子工程學研究所丁建裕Ding, Jian-YuJian-YuDing2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57557隨著數位應用及信號系統的大量增加，市場對於高速類比/數位轉換器的需求與日俱增。其中快閃式架構的類比/數位轉換器，適用於以高速要求為主，並且不需要高解析度的應用。舉例而言, 硬碟驅動系統的讀寫，通訊系統， 微波電子天文望遠鏡，以及每秒十億取樣的微波接收器，都屬於此應用範圍。 我們提出了一個五位元，每秒十億次取樣的類比/數位轉換器。其採用了分散式取樣，並且以數位補償製程不匹配所產生的偏差電壓。取樣的方式，是以電流模式的正反器(current-mode flipflops)來實現，由於取消了訊號路徑上的開關，故可避免來自於輸入訊號變化造成失真。我們以五位元的數位方式做校正偏差電壓。此轉換器是以0.18-μm金氧半電晶體製程製做，其差動及積分非線性失真分別是0.4及0.6 LSB。在10 GHz的取樣頻率下，其有效位數為4.05位元。本電路類比部份使用1.8伏特的電壓，包括時脈緩衝級的消耗功率為 560 mW 。晶片總面積為1.58 mm × 1.11 mm。With the increasing use of digital computing and signal processing, the need of high-speed ADCs increases with time. Flash ADCs are still the architecture of choice, where maximum sampling rate and need no high resolution. For example, read-write channel of a disk drive systems, communication systems, microwave telescope array, and 10-GSamples/s microwave receiver are the cases. A 5-b 10-GSample/s analog-to-digital converter incorporates distributed sampling and digital offset calibration techniques. The sampling is accomplished by current-mode flipflops, eliminating the input-dependent distortions. The offset is calibrated digitally with a resolution of 5 bits. Fabricated in 0.18-μm CMOS technology, this converter achieves differential and integral nonlinearities of 0.4 and 0.6 LSB, respectively, and 4.05 effective bits at a sampling rate of 10 GHz. The circuit consumes 560 mW from a 1.8-V supply and occupies an area of 1.58 mm × 1.11 mm including pads.Contents Chapter 1 Introduction..............................................1 1.1 Motivation................................................1 1.2 Thesis Organization.......................................2 Chapter 2 Fundamental of Analog-to-Digital Converters...............3 2.1 Performance Metrics...................................3 2.1.1 Resolution..........................................3 2.1.2 Sampling Rate.......................................3 2.1.3 DNL and INL.........................................4 2.1.4 SNR, THD, and SNDR..................................5 2.1.4 ENOB................................................8 2.2 Architectures for High-Speed A/D Converters...........9 2.2.1 Flash A/D Converter.................................9 2.2.2 Two-Step A/D Converter.............................11 2.2.3 Folding A/D Converter..............................11 2.2.4 Pipeline A/D Converter.............................13 2.3 Summary..............................................14 Chapter 3 Design of the 5-bit 10GS/s Analog-to-Digital Converter...15 3.1. Introduction........................................16 3.2. ADC ARCHITECTURE....................................16 3.2.1. Distributed Sampling..............................18 3.2.2 Offset Calibration.................................22 3.3. BUILDING BLOCKS.....................................27 3.3.1. Preamplifier......................................27 3.3.2 Flipflop...........................................30 3.3.3. Clock Buffer......................................31 3.3.4 Testing DAC........................................32 Chapter 4 Simulation, Layout, and Measurement Results.............34 4.1 Simulation and Layout................................34 4.1.1 Transient Simulation and Layout....................34 4.1.2 Monte-Carlo Simulation.............................37 4.2 Measurement Results..................................41 4.2.1 Statistic Testing..................................43 4.2.2 Dynamic Testing....................................48 4.3 Performance Summary..................................53 Chapter 5 Conclusions..............................................54 5.1Conclusions...........................................54 Bibliography.............................................553247434 bytesapplication/pdfen-US類比/數位轉換器分散式取樣偏差校正直接ADC-DAC測試A/D converterdistributed samplingoffset calibrationdirect ADC-DAC test.thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57557/1/ntu-95-R93943007-1.pdf