Lu, Yu ShengYu ShengLuChen, Kuan ChengKuan ChengChenHsu, Yu LingYu LingHsuYAO-WEN CHANG2023-06-152023-06-152022-07-1097814503914290738100Xhttps://scholars.lib.ntu.edu.tw/handle/123456789/632689The optical interconnection is a promising solution for on-chip signal communication in modern system-on-chip (SoC) and heterogeneous integration designs, providing large bandwidth and high-speed transmission with low power consumption. Previous works do not handle two main issues for on-chip optical-electrical (O-E) co-design: the thermal impact during O-E routing and the trade-offs among power consumption, wirelength, and congestion. As a result, the thermal-induced band shift might incur transmission malfunction; the power consumption estimation is inaccurate; thus, only suboptimal results are obtained. To remedy these disadvantages, we present a thermal-aware optical-electrical routing co-design flow to minimize power consumption, thermal impact, and wirelength. Experimental results based on the ISPD 2019 contest benchmarks show that our co-design flow significantly outperforms state-of-the-art works in power consumption, thermal impact, and wire-length.[SDGs]SDG7conference paper10.1145/3489517.35304042-s2.0-85137419347https://api.elsevier.com/content/abstract/scopus_id/85137419347