Fang, Hung-ChiHung-ChiFangChang, Yu-WeiYu-WeiChangWang, Tu-ChihTu-ChihWangLian, Chung-JrChung-JrLianLIANG-GEE CHEN2009-02-252018-07-062009-02-252018-07-06200510518215http://ntur.lib.ntu.edu.tw//handle/246246/141450https://www.scopus.com/inward/record.uri?eid=2-s2.0-27644533964&doi=10.1109%2fTCSVT.2005.852618&partnerID=40&md5=c7af7780e17dc7f1578060e81b6a5218This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s. © 2005 IEEE.application/pdf1013039 bytesapplication/pdfen-USDiscrete wavelet transform (DWT); Ebc with optimized truncation (EBCOT); Embedded block coding (EBC); Image processing; JPEG 2000; Parallel processingDiscrete wavelet transforms (DWT); Ebc with optimized truncation (EBCOT); Embedded block coding (EBC); JPEG 2000; Parallel processing; Computer architecture; Computer science; Embedded systems; Encoding (symbols); Information technology; Optimization; Parallel processing systems; Wavelet transforms; Block codesjournal article10.1109/TCSVT.2005.8526182-s2.0-27644533964http://ntur.lib.ntu.edu.tw/bitstream/246246/141450/1/37.pdf