Chou M.-HSHEN-IUAN LIU2021-09-022021-09-02202010638210https://www.scopus.com/inward/record.uri?eid=2-s2.0-85094919885&doi=10.1109%2fTVLSI.2020.3014885&partnerID=40&md5=8208af52d1fd6d9837d5673f23cb3bb9https://scholars.lib.ntu.edu.tw/handle/123456789/581138A 2.4-GHz area-efficient and fast-locking subharmonically injection-locked type-I phase-locked loop (SIL-TPLL) is presented. A timing-adjusted phase detector (TPD) is proposed to calibrate the injection timing. This TPD also reduces the settling time of the SIL-TPLL. The loop capacitance of the type-I PLL is tiny to save the area. This SIL-TPLL is fabricated in 45-nm CMOS technology. Its active area is 0.013 mm2. The power consumption is 5.6 mW at 2.4 GHz for a supply of 0.87 V. The integrated jitter of the SIL-TPLL over 1 kHz to 40 MHz is 0.91 ps. ? 1993-2012 IEEE.Phase comparators; Active area; Area-Efficient; CMOS technology; Fast-locking; Injection locked; Injection timing; Phase detectors; Settling time; Phase locked loopsjournal article10.1109/TVLSI.2020.30148852-s2.0-85094919885