Chan, W.-K.W.-K.ChanChang, J.-Y.J.-Y.ChangChen, T.-W.T.-W.ChenTseng, Y.-H.Y.-H.TsengSHAO-YI CHIEN2018-09-102018-09-10200910518215http://www.scopus.com/inward/record.url?eid=2-s2.0-67249101533&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/350334In the next-generation visual surveillance systems, content analysis tools will be integrated. In this paper, to accelerate these tools, it is proposed to integrate a hardware content analysis engine into a smart camera system-on-a-chip (SoC). A smart camera SoC hardware architecture with the proposed visual content analysis engine is first presented. This engine consists of dedicated accelerators and a programmable morphology coprocessor. Stream processing design concept, framelevel pipelining, and subword level parallelism are employed together to efficiently utilize the bandwidth of the system bus and achieve high throughput. The implementation results show that, with 168 K logic gates and 40.63 Kb on-chip memory, a processing speed of 30 640 × 480 frames/s can be achieved, while the operations of video object segmentation, object description and tracking, and face detection and scoring are supported. © 2009 IEEE.Co-processor; Content analysis; Content analysis engine; Face Detection; Hardware architecture; High throughput; Object description; On chip memory; Processing speed; Smart camera; Smart cameras; Stream processing; Subword; Surveillance; System bus; System-on-a-chip; Video-object segmentation; Visual content; Visual surveillance; Visual surveillance systems; Application specific integrated circuits; Cameras; Engines; Image coding; Microprocessor chips; Monitoring; Programmable logic controllers; Visual communication; Security systemsjournal article10.1109/TCSVT.2009.20174082-s2.0-67249101533