Optimal design of megabyte second-level caches for minimizing bus traffic in shared-memory shared-bus multiprocessors

Dept. of Comput. Sci., & Inf. Eng., National Taiwan Univ.Oyang, Yen-JenYen-JenOyangWu, Le-ChunLe-ChunWu2007-04-192018-07-052007-04-192018-07-051992-01http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032303application/pdf462938 bytesapplication/pdfen-USOptimal design of megabyte second-level caches for minimizing bus traffic in shared-memory shared-bus multiprocessorsjournal article10.1109/HICSS.1992.183196http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032303/1/00183196.pdf