Huang, Mu-ChenMu-ChenHuangSHEN-IUAN LIU2011-10-072018-07-102011-10-072018-07-10201015497747http://scholars.lib.ntu.edu.tw/handle/123456789/359283http://ntur.lib.ntu.edu.tw/bitstream/246246/237189/-1/03.pdfhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-76149138450&doi=10.1109%2fTCSII.2009.2037259&partnerID=40&md5=041665f9eb9126832971ed652bb6278cA 10-MS/s-to-100-kS/s power-scalable fully differential comparator-based switched-capacitor (CBSC) 10-bit pipelined analog-to-digital converter (ADC) is presented. To operate over a wide range of sampling rates, an adaptive biasing technique is proposed to enhance both linearity and signal-to-noise- plusdistortion ratio (SNDR) at low sampling rates. This ADC has been fabricated in a 0.18-μm standard CMOS process. It achieves 62.3-dB spurious-free-dynamic range (SFDR) and 53.3-dB SNDR while being sampled at 10 MS/s and consuming 1.95 mW from a 1.8-V power supply, which obtains a figure of merit of 510 fJ/step. With the utilization of adaptive biasing, the SNDR increases from 53.3 to 56.4 dB at most when decreasing the sampling rate. In addition, its power consumption continuously reduces from 1.95 mW (10 MS/s) to 158.4 μW (100 kS/s). © 2006 IEEE.CBSC circuits; Comparator-based switched capacitor (CBSC); Pipelined analog-to-digital converter (ADC); Power scalable[SDGs]SDG7Comparator circuits; Comparators (optical); Frequency converters; Pipelines; Signal to noise ratio; Adaptive biasing; Figure of merits; Fully differential; Pipelined analog-to-digital converter; Power scalable; Spurious free dynamic range; Standard CMOS process; Switched capacitor; Analog to digital conversionjournal article10.1109/TCSII.2009.20372592-s2.0-76149138450http://ntur.lib.ntu.edu.tw/bitstream/246246/237189/-1/03.pdf