Graduate Inst. of Electron. Eng., National Taiwan Univ.Fang, Hung-ChiHung-ChiFangWang, Tu-ChihTu-ChihWangLIANG-GEE CHEN2007-04-192018-07-062007-04-192018-07-062002-10http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021068https://www.scopus.com/inward/record.uri?eid=2-s2.0-4344670908&doi=10.1109%2fAPCCAS.2002.1115058&partnerID=40&md5=72bdee23d5c75e9e581dba4623ac58a3This paper presents a deblocking filter architecture in the MPEG-4 standard. This architecture performs as a 1D nonlinear filter across the block boundary to efficiently suppress blocking artifacts. Two shift register banks are used in the design; their use greatly reduces the control complexity of data flow. Due to efficient scheduling, the size of storage and the total clock cycles are minimized. The maximum processing rate of this architecture mapped in 0.35 μm technology is 30 Mpixels/sec, which can support NTSC resolution at 30 frames per second. The power consumption of the design is 46.6 mW while operating frequency is 81 MHz. © 2002 IEEE.application/pdf491973 bytesapplication/pdfen-USDesign engineering; Digital signal processing; Discrete cosine transforms; Filtering; Iterative algorithms; Low pass filters; MPEG 4 Standard; Quadratic programming; Quantization; Real time systemsAlgorithms; Cosine transforms; Digital signal processing; Digital storage; Discrete cosine transforms; Filtration; Interactive computer systems; Iterative methods; Low pass filters; Motion Picture Experts Group standards; Quadratic programming; Quantization (signal); Shift registers; Signal processing; Deblocking filters; Design Engineering; Efficient scheduling; Iterative algorithm; MPEG-4 standard; Operating frequency; Quantization; Real-time deblocking; Real time systemsconference paper10.1109/APCCAS.2002.11150582-s2.0-4344670908http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021068/1/01115058.pdf