Hu, Y.-S.Y.-S.HuHuang, P.-C.P.-C.HuangYang, M.-T.M.-T.YangWu, S.-W.S.-W.WuHSIN-SHU CHEN2020-06-112020-06-112017https://scholars.lib.ntu.edu.tw/handle/123456789/501233An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR sub-ADC low-power, but also accelerates its conversion rate. A self-trigger latch (STL) technique is also used to reduce digital power consumption. The prototype ADC in 40nm CMOS consumes 3.1mW at 1.5GS/s with a 0.9V supply. It achieves a Nyquist SNDR of 44.5dB and results in an FoM of 15fJ/c.-s. © 2016 IEEE.Analog-to-digital converter (ADC); charge sharing; energy-efficient; low-skew demultiplexer; self-triggered latch; successive-approximation register (SAR); two-step[SDGs]SDG7Clocks; Demultiplexing; Electric power utilization; Energy efficiency; Analog to digital converters; Charge sharing; Demultiplexers; Energy efficient; self-triggered latch; Successive approximation register; two-step; Analog to digital conversionconference paper10.1109/ASSCC.2016.78441402-s2.0-85015160836https://www.scopus.com/inward/record.uri?eid=2-s2.0-85015160836&doi=10.1109%2fASSCC.2016.7844140&partnerID=40&md5=02dfffe1bb45b40ca77a99e8ef999ca9