Liu, C.-Y.C.-Y.LiuLuo, T.-N.T.-N.LuoHeo, D.D.HeoYI-JAN EMERY CHEN2018-09-102018-09-10200615311309http://www.scopus.com/inward/record.url?eid=2-s2.0-33750841288&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/321714A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-μm CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3 V, the P 1 dB and associated power-added-efficiency (PAE) of the PA are 21 dBm and 33%, respectively. At the output power 6-dB backoff from P 1 dB, the PAE remains 21 %. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio. © 2006 IEEE.Adaptive bias; CMOS; Doherty power amplifler (PA); Orthorgonal frequency division multiplexing (OFDM); Peak-to-average power ratio (PAPR)Adaptive bias; Doherty power amplifiers (PA); Peak-to-average power ratio (PAPR); Adaptive control systems; CMOS integrated circuits; Orthogonal frequency division multiplexing; Power amplifiersjournal article10.1109/LMWC.2006.8849092-s2.0-33750841288