Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memory

H.-H. ChuangS.-J. WuM.-Z. HongD. HsuR. HuangTZONG-LIN WU2018-09-102018-09-102008-12http://scholars.lib.ntu.edu.tw/handle/123456789/342781Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memoryconference paper10.1109/EDAPS.2008.47359912-s2.0-60649099216