Lin T.-LSAO-JIE CHEN2023-06-092023-06-09202021641676https://www.scopus.com/inward/record.uri?eid=2-s2.0-85115304854&doi=10.1109%2fSOCC49529.2020.9524768&partnerID=40&md5=c174a23e7b8ca6d9fbda003b93f1d3b4https://scholars.lib.ntu.edu.tw/handle/123456789/632366A novel scheme, spatially-correlated Design Dependent Critical-Path Monitor (DDCPM), is proposed, which can provide valuable references in deriving application-specific, process- and temperature-aware DVFS for aggressive power saving during runtime. Such DDCPM utilizes its unique spatial correlation feature and real-time sampling techniques to precisely sense the unexpected behavior introduced by over-scaled voltage under the operating conditions with random and mutually dependent Process-Voltage-Temperature (PVT) variations in each individual chip. Our experimental results obtained in two IPs implemented in TSMC 28 nm process node respectively show average step-wise 7.80% and 8.19% power could be reduced at a smaller granular level of voltage scaling, which corresponding maximum power reductions, 55.6% and 57.5% in Typical Corner could be finally achieved. © 2020 IEEE.Design Dependent Critical-Path Monitor (DDCPM); System Control and Management Interface (SCMI)Dynamic frequency scaling; Timing circuits; Uninterruptible power systems; Control and management; Control interfaces; Critical path monitor; Design dependent critical-path monitor; Management interfaces; Spatial correlations; System control; System control and management interface; Systems management; Temperature variation; Voltage scalingconference paper10.1109/SOCC49529.2020.95247682-s2.0-85115304854