劉深淵臺灣大學：電子工程學研究所吳家豪Wu, Jia-HaoJia-HaoWu2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57591隨著CMOS製程技術的發展與進步，以往需要以BJT實現的高速電路也漸漸被整合性較高的CMOS所取代。在短程通訊中，高速電路的需求越來越高，尤其是在未開放的57GHz至64GHz這頻帶，吸引越來越多人來研究開發。 在高速電路中，被動電感的使用已經越來越頻繁了，但元件的準確性仍然是一大問題。以鎖相迴路為例，若電感值預估或大或小，再加上製程的偏移，可能導致壓控振盪器的可調範圍無法與除頻器的可除頻範圍相互重疊，這將會導致回授訊號的不正確而使整個迴路無法鎖定。要解決這個問題最主要的方法就是增大除頻器的可除頻範圍，本論文將提出幾種架構來增大可除頻範圍。 在論文中將會推導出可除頻範圍與注入電流的關係，若注入的電流越大，則可除頻範圍也會隨之增大。但往往由於寄生電容在高頻時的效應變大而使得注入電流會有所損失，因此提出的第一個架構便以減少漏電流為目標，此架構的原理為以電感共振掉寄生電容進而減少漏電流。第二個及第三個架構則是在等效上增加電流，彌補漏電流的不足。 除了針對可除頻範圍做改進，我們也提出一個可應用於40GHz及60GHz的多頻帶除頻器。傳統上要以切電容或切電感方式達到如此大的頻帶，不僅需耗費相當大的面積，而且過多的電容也可能導致除頻器無法運作。在這裡我們提出一個將多個電感整合的方式，只需以一個電感的面積便可切換不同的頻帶。 在前述中已提及高速鎖相迴路可能面臨的問題，在這裡我們提出一個以二位法搜尋法為基礎的鎖相迴路。此鎖相迴路的特色是以切電容的方式來增加可除頻範圍，並是以一數位迴路來自動搜尋所需的頻帶；此外，在輸出則採用倍頻器使得壓控振盪器及除頻器只需設計在30GHz即可，以減少電感模型在過高頻率的不準確性。最後整個迴路成功地鎖定在64.33GHz至66.22GHz的範圍。With the development and progress of CMOS process, the high-speed circuits should be realized by BJT in the past are gradually replaced by CMOS. In short channel communications, the demand for the high-speed circuits is higher and higher, especially the unlicensed band, 57GHz to 64GHz, which attracts more and more research. In high-speed circuits, passive inductors are frequently used, but the accuracy of those devices is still a problem. Take PLLs for example, if estimated inductance is too much or less, and with the process variation, it will lead to the non-overlap between VCO and divider and the incorrect feedback signal and the loop will fail to lock. The basic method to solve this problem is to widen the locking-range of divider. This thesis will propose some architecture to enhance the locking-range. It will derive the relation between the locking-range and injected-current in this thesis. The larger the injected-current is, the wider the locking-range is. But it often loses some current due to the parasitic capacitors. Therefore, the purpose of the first proposed architecture is to reduce leakage current based on inductors resonating with capacitors. The second and third architecture are adding extra current in order to compensate the loss of leakage current. In addition to improvement for the locking-range, we also propose a multi-band divider which can be applied to 40GHz and 60GHz systems at the same time. Traditionally, it needs to switch capacitors or inductors to achieve such wide frequency band. It not only occupies large chip area but also too much capacitor may cause the divider fail to work. In this thesis, we propose a method to integrate many inductors together and we can switch different frequency bands only with one inductor area. It has been mentioned what problems high-speed PLLs might face previously. In this thesis we propose a PLL based on the binary-search scheme. The characteristic of this PLL is to use a digital circuit to automatically search the needed frequency band, which is derived from switching capacitors. Besides, the output frequency is doubled by the frequency doubler, which lets the VCO and divider only designed at 30GHz to reduce the inaccuracy of the inductor model at too high frequency. Finally, this PLL successfully locks at the range from 64.33GHz to 66.22GHz.Abstract ………………………………………………………… I Contents ………………………………………………………… V List of Figures ………………………………………………………… VII List of Tables ………………………………………………………… XV 1 Introduction 1 1.1 Motivation …………………………………………… 1 1.2 Thesis Organization ……………………………… 2 2 The Basics of Phase-Locked Loops 5 2.1 Phase-Locked Loop (PLL) Fundamentals ………… 6 2.1.1 Phase-Frequency Detector (PFD) ………………… 6 2.1.2 Charge Pump (CP) …………………………………… 9 2.1.3 Voltage-Controlled Oscillator (VCO) ………… 12 2.1.4 Loop Filter ………………………………………… 13 2.1.5 Frequency Divider ………………………………… 15 2.2 Phase Noise Performance Analysis ……………… 18 2.2.1 Noise at Input ……………………………………… 20 2.2.2 Noise of the VCO …………………………………… 22 2.3 Charge-Pump PLL Design …………………………… 23 2.3.1 Second-Order PLL …………………………………… 23 2.3.2 Third-Order PLL …………………………………… 26 2.3.3 Fourth-Order PLL …………………………………… 29 2.4 Architecture Simulation ………………………… 32 3 Categories of Frequency Dividers 35 3.1 Flip Flop-Based Frequency Divider …………… 36 3.1.1 Digital NAND Gates-Based Frequency Divider … 37 3.1.2 True Single-Phase Clock Frequency Divider … 39 3.1.3 Current-Mode Logic (CML)-Based Frequency Divider ……… 41 3.2 Miller Divider ………………………………………………………… 44 3.3 Analysis of CML-Based Frequency Dividers …… 46 4 Locking-Range Enhancement Technique 53 4.1 CML-Based Dividers with Shunt-Peaking Technique ……… 55 4.1.1 Circuit Architecture ……………………………… 55 4.1.2 Simulation Results and Chip Layout …………… 57 4.1.3 Measurement Results ……………………………… 60 4.2 CML-Based Dividers with Current-Reused Technique ………… 63 4.2.1 Circuit Architecture ……………………………… 63 4.2.2 Simulation Results and Chip Layout …………… 65 4.2.3 Measurement Results …………………………………67 4.3 CML-Based Dividers with gm-Boosted Technique 70 4.3.1 Circuit Architecture ……………………………… 70 4.3.2 Simulation Results and Chip Layout …………… 72 4.3.3 Measurement Results …………………………………75 4.4 Multi-Band CML-Based Dividers ………………… 79 4.4.1 Circuit Architecture ……………………………… 79 4.4.2 Simulation Results and Chip Layout …………… 81 4.4.3 Measurement Results ……………………………… 84 5 A 64.3-66.2GHz Digitally-Calibrated PLL 89 5.1 A Digitally-Calibrated PLL’s Architecture … 90 5.2 Circuit Implementation …………………………… 92 5.2.1 Phase-Frequency Detector ………………………… 92 5.2.2 Charge Pump and Loop Filter …………………… 93 5.2.3 Frequency Detector, Lock Detector and Reset Controller …… 95 5.2.4 VCO and Frequency Doubler ……………………… 98 5.2.5 Frequency Dividers ………………………………… 101 5.2.6 Successively Approximation Register (SAR) … 103 5.3 Simulation Results and Chip Layout …………… 105 5.3.1 Behavior Simulation ……………………………… 105 5.3.2 Circuit-Level Simulation ………………………… 107 5.4 Measurement Results ……………………………… 110 6 Conclusions 117 Appendix A A Digitally-Calibrated PLL with Divided-by-3 Divider 119 Bibliography ……………………………………………… 133en-US除頻器鎖相迴路frequency dividersphase-locked loopsSARthesis