Dept. of Electr. Eng., National Taiwan Univ.SHEN-IUAN LIU2007-04-192018-07-062007-04-192018-07-061994-1200135194http://ntur.lib.ntu.edu.tw//handle/246246/2007041910042620https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028768768&doi=10.1049%2fel%3a19941427&partnerID=40&md5=9ce3271e55884ed41f169ed52986323bA new low voltage CMOS four-quadrant multiplier is presented. Simulation results show that, for a power supply of ±1.5V the differential linear range is over ±0.8V with the linearity error less than 2%. The total harmonic distortion is less than 1% with the input range up to ±0.6V, The simulated -3dB bandwidth of this multiplier is about 12MHz. The proposed circuit is expected to be useful in low-voltage analogue signal processing applications. © 1994, IEE. All rights reserved.application/pdf204913 bytesapplication/pdfen-USCMOS integrated circuits; Multiplying circuitsBuffer circuits; CMOS integrated circuits; Computer simulation; Electric current control; Frequency stability; Gain control; Harmonic analysis; Integrated circuit layout; Transistors; Triodes; VLSI circuits; Voltage control; Four quadrant multiplier; Harmonic distortion; Software package SPICE; Multiplying circuitsjournal article10.1049/el:199414272-s2.0-0028768768http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910042620/1/00350154.pdf