Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine

Wu, C.-H.C.-H.WuChen, T.-S.T.-S.ChenLee, D.-Y.D.-Y.LeeLiu, T.-T.T.-T.LiuWu, A.-Y.A.-Y.WuTSUNG-TE LIU2020-06-112020-06-112017https://scholars.lib.ntu.edu.tw/handle/123456789/499795[SDGs]SDG7Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engineconference paper10.1109/VLSI-DAT.2017.79396412-s2.0-85021411330https://www.scopus.com/inward/record.uri?eid=2-s2.0-85021411330&doi=10.1109%2fVLSI-DAT.2017.7939641&partnerID=40&md5=c276d0ae3c69f6a70c279b0dfb61f2e4