吳安宇臺灣大學：電子工程學研究所沈佩玲Shen, Pei-LingPei-LingShen2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57303近年來，無線通訊的市場蓬勃發展，服務也越來越多元化。對於通訊的需求從原本的通話，增加到資料的傳輸、甚至於多媒體服務。因應不同的傳輸性質、傳輸速率，第三代行動通訊系統制定了兩種錯誤更正碼的編碼方式，分別為迴旋編碼及渦輪編碼。因此，在錯誤更正碼的編/解碼器設計上，便需要兩種不同的理論與架構。一般，在硬體的實現上，最直覺的方法就是為兩種不同的解碼器架構分別設計相對應的硬體來實現其弁遄F然而這樣的作法會有硬體面積高、硬體使用率低，而與行動通訊所強調的“輕巧”相違背。在已發表的研究裡面,少數提出符合第三代行動通訊規範的設計,但也僅止於重新規劃硬體架構。 在我們的研究中，除了利用兩者硬體架構上的相似性作整體架構規劃外，更進一步根據解碼時序的分析，達到系統化降低解碼時間、硬體面積以及硬體使用率的目標。我們的設計特別能有效縮短混合渦輪碼及迴旋碼之資料流的解碼時間。 最後,我們以硬體描述語言撰寫此架構，實現了此適用於第三代行動通訊系統之三模式(迴旋碼,渦輪碼,迴旋碼渦輪碼)通道解碼器的設計,並以0.18um製程實作晶片，在最高的工作時脈100MHz下，固定六次迴圈渦輪碼解碼模式可輸出每秒4.17MHz的資料流。The needs of 3rd generation mobile communication system (3G) and its multi-media services are growing in the near feature. One of key element in 3G is channel coding. Channel coding minimizes the effects of noise and interference on the transmitted signal at the physical layer. According to the 3rd Generation Partnership Project (3GPP) technical specification two channel coding scheme, turbo code and convolutional code, are applied. Both of these channel coding schemes are typically computationally intensive and power-consuming tasks and is therefore normally implemented in a dedicated hardware block. In 3G system, the voice and data streams use convolutional and turbo code schemes, respectively. Typically, the corresponding convolutional and turbo code decoder are built separately. In the state of art, dual-mode designs combine hardware of those two decoder. However, there is no combination timing of two algorithms. The objective of this thesis is based on a methodology of associate timing and hardware in two decoding algorithms, then implement an FEC kernel which complaint with 3Gpp standard. After exploiting the fact that both convolutional and turbo decoders are based on similar trellis decoders, we built both decoding operations in one single architecture to achieve hardware association; besides, we propose a triple-mode (convolutional decoding, turbo decoding and convolutional decoding while turbo decoding) timing charts by complementing idle time of each other. This results in a reduced cost solution through resource sharing. Finally, we implemented this design in Artisan 0.18 cell-library. This FEC kernel run at clock rate equals 100MHz, and decodes a 4.18Mbps turbo encoded data stream with 6 iterations.List of Table xiv Chap 1 Introduction 1 1.1 Motivation and Goal 1 1.2 Design Specification 1 Chap 2 Introduction of Viterbi Algorithm 4 2.1 Viterbi Algorithm 4 2.2 Timing Chart of Viterbi Decoding 5 Chap 3 Introduction of MAP Algorithm 9 3.1 MAP Algorithm 9 3.2 Log-MAP algorithm 10 3.3 Timing Chart of MAP decoding 11 Chap 4 Triple-Mode Decoder in Timing and Hardware Analysis 13 4.1 Timing Association and MAP/VA mode 13 4.2 Proposed Architecture of Triple-Mode Kernel 15 4.4.1 Hardware Association 16 4.3 MAP/VA mode 19 4.4 VA Mode 20 4.5 MAP Mode 21 Chap 5 DSP Modules of Triple-Mode MAP/VA kernel 23 5.1 GAMMA/ BM module 23 5.2 Encoder Embedded Trellis Router (EETR) 26 5.2.1 VA Mode 26 5.2.2 MAP Mode 28 5.3 RUA/PM module 30 5.4 Trace Back Unit (TB) 31 Chap 6 Fixed Point Analysis of Log-MAP Decoder 34 6.1 Quantization of Received Bits 34 6.2 Quantization of1014117 bytesapplication/pdfen-US維特比演算法渦輪碼Turbo CodeViterbi Algorithmthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57303/1/ntu-93-R91943115-1.pdf