Shao-Ku KaoSHEN-IUAN LIU2018-09-102018-09-102008-1015497747http://scholars.lib.ntu.edu.tw/handle/123456789/342651https://www.scopus.com/inward/record.uri?eid=2-s2.0-55649085517&doi=10.1109%2fTCSII.2008.925664&partnerID=40&md5=0c7b4ef1c59bc5f6240f4fc84464472aA delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18-μm CMOS process. Its active area is 0.078 mm2. The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz. © 2008 IEEE.Calibration; Charge pump circuits; Clocks; Errors; Active area; Background calibrations; Charge pump; CMOS processs; Delay-locked loops; Input and outputs; Phase error; Static phase errors; Delay lock loops[SDGs]SDG7Calibration; Charge pump circuits; Clocks; Errors; Active area; Background calibrations; Charge pump; CMOS processs; Delay-locked loops; Input and outputs; Phase error; Static phase errors; Delay lock loopsjournal article10.1109/TCSII.2008.9256642-s2.0-55649085517WOS:000260385300001