陳信樹臺灣大學:電機工程學研究所黃健群Huang, Chien-ChunChien-ChunHuang2010-07-012018-07-062010-07-012018-07-062009U0001-0108200901081200http://ntur.lib.ntu.edu.tw//handle/246246/188037這篇論文的提出了一個高速八位元電流引導式數位類比轉換器，使用區段化電流切換式架構，其中包含高五位元的溫度計碼及低三位元的二進制碼，這樣的設計不僅可以保持原本電流切換式架構的優點，更可以達到降低消耗功率的好處。這次設計的數位類比轉換器其架構是使用所提出的新的開關切換順序方式來實現。這個新的開關切換方式是將高位元的電流源分成八個部份來補償二次誤差並且使用整體非線性失真邊界演算法來達到最佳化的目的。　這個數位類比轉換器採用UMC 90nm 1P9M mixed-signal CMOS製程來實現，整體晶片核心面積為0.013mm2，加入PADs之後0.415mm2。整體非線性失真及差動非線性失真分別為0.19LSB和0.26LSB。當操作在10億赫茲及輸入頻率為9.25百萬億赫茲時，其無雜散動態範圍達到49.2dB。功率消耗在1伏操作下為8.2毫瓦。This thesis proposes an 8-bit 1GHz digital-to-analog converter with a segmented current steering architecture that consists of two parts, the upper 5-bit thermometer code and the lower 3-bit binary-weighted code. The design not only keeps the advantages of current steering architecture, but also consumes lower power. The DAC architecture is implemented by the proposed switching sequence. The new switching sequence divides the upper 5-bit current source into eight unary current source to compensate quadratic error and also uses integral non-linear (INL) bounded algorithm to optimize the INL characteristic. This DAC has been implemented in a 90nm 1P9M mixed-signal CMOS process provided by UMC, with active area of 0.013mm2 and total area including PADs is 0.415mm2.The INL and differential non-linear (DNL) are 0.19 and 0.26 LSB, respectively. The spurious-free dynamic range (SFDR) is 49.2dB when the update rate is 1GHz and the input frequency is 9.25MHz. The power consumption is 8.2mW with a supply voltage of 1V.中文摘要...................................................Ibstract.................................................IIIontents...................................................Vist of Figures...........................................IXist of Tables..........................................XIIIhapter 1 Introduction....................................1.1 Motivation.............................................1.2 Thesis Organization....................................2hapter 2 Fundamental Concepts and Architectures of DAC...3.1 Introduction...........................................3.2 Ideal DAC..............................................4.3 Static Performance.....................................5.4 Dynamic Performance....................................8.5 Frequency Domain Performance..........................11.6 Digital-to-Analog Converter Architecture..............13.6.1 Resistor-String DAC.................................14.6.2 R-2R Ladder DAC.....................................15.6.3 Charge Redistribution DAC...........................16.6.4 Current-Steering DAC................................17.6.5 Segmented architecture DAC..........................19hapter 3 Circuit Design Techniques of Current-Steering DAC.......................................................21.1 Digital Circuit Design................................21.1.1 Segmentation of Current-Steering DAC................22.1.2 The Proposed DAC Architecture.......................27.1.3 TSPC DFF............................................29.1.4 Binary-Thermometer Decoder..........................30.1.5 Deglitch Latch......................................31.1.6 Clock Tree..........................................33.2 Analog Circuit Design.................................34.2.1 Design flow of Unit Current Source..................34.2.1.1 INL Yield.........................................35.2.1.2 Random Error......................................38.2.1.3 Finite Output Impedance of Current Source.........40.2.2 Bias Circuit........................................43.3 The Proposed Switching Sequence of Current Source Array to Compensate Quadratic Error.............................45.3.1 Systematic Error....................................45.3.2 Quad Quadrant Switching Sequence....................47.3.3 The Proposed Switching Sequence.....................49.3.4 The Proposed Switching Sequence with INL Bounded Algorithm.................................................50.4 Layout Implementation.................................55.5 Simulation Results....................................58hapter 4 Chip Measurement Results.......................61.1 Evaluation Board Design...............................61.1.1 Grounding...........................................63.1.2 Bypassing and Decoupling............................64.1.3 Digital Input and Analog Output.....................65.2 Measurement Setup.....................................66.2.1 Static Measurement Setup............................66.2.2 Dynamic Measurement Setup...........................67.3 Measurement Results...................................68.3.1 Static Measurement Results..........................68.3.2 Dynamic Measurement Results.........................69hapter 5 Conclusion and Future Work.....................75.1 Conclusion............................................75.2 Futrue Work...........................................76eferences................................................773883479 bytesapplication/pdfen-US數位類比轉換整體非線性失真整體非線性邊界演算法差動非線性失真無雜散動態範圍digital-to-analog converterintegral non-linearintegral non-integral bounded algorithmdifferential non-linearspurious-free dynamic rangethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188037/1/ntu-98-J95921038-1.pdf