電機資訊學院: 電子工程學研究所指導教授: 陳信樹廖柏詩Liao, Bo-ShiBo-ShiLiao2017-03-062018-07-102017-03-062018-07-102016http://ntur.lib.ntu.edu.tw//handle/246246/276101類比數位轉換器在電子系統中扮演極重要的角色，它是自然界類比信號與數位信號中間的橋梁。近年來低功率的電子產品的需求越來越高，特別是應用在無線通訊、感應器與生醫系統中，所以如何降低類比數位轉換器的耗電儼然成為一個非常熱門的題目。在各種不同的架構中，連續漸進式式類比數位轉換器不需要放大器且內部架構大部分都是數位電路，因此可以達到低功率下運作的要求。 在低功率類比數位轉換器研究中，提出了一個十二位元每秒一千萬次取樣的連續漸進式類比至數位轉換器與一個七位元每秒二十億次取樣的免校正時間交錯式的類比至數位轉換器。本論文第一部份提出一個小單位電容值和簡單控制邏輯電路，運用在高電能效率高解析度連續漸進式類比數位轉換器當中，結合了一個可以容忍錯誤的任意電容權重的電容陣列與差動控制邏輯來減少電路複雜度。此技巧驗證於台積電低壓40奈米製程。此作品工作電壓為0.9伏特，單通道轉換速度為每秒一千萬次，功率消耗只有36.9微瓦，在經過晶片外的校正後獲得低輸入頻率下10.05的有效位元，FoM達3.48fJ/conversion-step。 在第二個設計中，為了解決偏移電壓不匹配之問題，採用了一個偏移電壓補償演算法，把通道間偏移電壓的不匹配轉換成非線性度，再透過創造保護區間去補償。此外，為了減少時序不匹配之問題，實施了一個前端取樣電路將影響去除。因此，此時間交錯式的類比數位轉換器無須校正，在每秒二十億次的轉換之下，功率消耗為24.8mW，FoM為117 fJ/conversion-step。Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power specification. In the field of low power SAR ADC, an 12-bit 10MS/s single-channel SAR and 7-bit 2GS/s calibration-free time-interleaved ADC are presented. This thesis first proposes an energy-efficient high resolution SAR ADC with small unit capacitance and simple controller logic. In order to save digital power, it combined with arbitrary capacitor array, which tolerates errors of dynamic offset and capacitor settling in MSBs during conversion and a differential control logic circuit are proposed to decrease the circuit complexity. The technique are verified by TSMC 1P6M3X1Z1U 40nm Low Power CMOS process. This work operates at 10MS/s in 0.9V supply voltage. Its power dissipation is only 36.9μW and gets 10.05 bit ENOB performance after off-chip calibration with low-frequency input. As the result, the peak FoM performance is 3.48fJ/conversion-step. In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it. In addition, a front-end track-and-hold circuit is implemented in order to eliminate time skew mismatch. This time-interleaved ADC in 55nm CMOS technology post-simulation achieves an ENOB of 6.8 and consumes 24.8mW. It results in a FoM of 117fJ/conversion-step.論文使用權限: 不同意授權類比/數位轉換器連續漸進式低功率高速時間交錯式偏移電壓不匹配時序不匹配無校正ADCSAR ADClow powerhigh speedtime-interleavedoffset mismatchtime skew mismatchcalibration-freethesis10.6342/NTU201600362