黃俊郎Huang, Jiun-Lang臺灣大學:電子工程學研究所邱柏薰Chiu, Po-HsunPo-HsunChiu2010-07-142018-07-102010-07-142018-07-102009U0001-2703200918500700http://ntur.lib.ntu.edu.tw//handle/246246/189180隨著顯示技術的發展與消費需求的增加，輕、薄、短、小跟低功率已經變成現在顯示器的兩大發展趨勢。其中一個縮小面積的方法是將周邊的閘極驅動器整合在面板上。在這篇論文中，我們提出了一個針對這種方法的低功耗閘極驅動器電路。這種電路設計可以大幅的降低功率消耗並且幫助穩定浮動閘線。With the recent advance in display technology and consumer demands, compact form factor and low power consumption has become the trend of modern displays. One popular approach to reduce the form factor is to integrate the gate drivers on the same glass as the display. In this thesis, we propose a low power gate driver design for such displays. It not only substantially lowers the power consumption but also help stabilize the floating gate lines.Contents_______________________________________謝 I要 IIbstract IIIontents IVhapter 1 Introduction 1.1 Motivation 1.2 Contribution 5.3 Thesis Structure 6hapter 2 Preliminaries 7.1 TFT-LCD Driving Circuitry 7.1.1 Data Driver 7.1.2 Scan Driver 10.2 Low Power Circuit Design 13.2.1 Low Power Level Shift with Pulse Source and Bootstrapped Capacitor 13.2.2 Reducing Power in Flexible a-Si:H Digital Circuits While Preserving State 17.2.1 The Clock-Gated Ring Counter 21hapter 3 The Proposed Techniques 27.1 A-Si:H TFT Gate Driver Architecture 27.2 The Clock-Gating Circuit 31.2.1 The C-element 31.2.2 Switches 34.3 Power Reduction Estimation 35hapter 4 Simulation Results 39.1 The Clock-Gating Circuit 39.2 The Gate Driver Output 41.3 The Floating Gate-Line Fluctuation Attenuation 43.4 Power Reduction 47.5 Area overhead 49hapter 5 Experimental Result 51.1 The Clock-Gating Circuit 53.1.1 Inverter 53.2 The Gate-Line and Gate Driver Output 57.3 Short Circuits Test 59.4 Summary of Experimental Result 60hapter 6 Conclusion and Further Work 63.1 Conclusion 63.2 Further Work 63eferences 641876078 bytesapplication/pdfen-US閘極驅動器低功率浮動閘線gate driverslow powerfloating gate linethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189180/1/ntu-98-R95943102-1.pdf