Zhu, ZiranZiranZhuMei, YangjieYangjieMeiLi, ZijunZijunLiLin, JingwenJingwenLinChen, JianliJianliChenYang, JunJunYangYAO-WEN CHANG2023-06-152023-06-152022-07-1097814503914290738100Xhttps://scholars.lib.ntu.edu.tw/handle/123456789/632692With the increasing complexity of the field-programmable gate array (FPGA) architecture, heterogeneity and clock constraints have greatly challenged FPGA placement. In this paper, we present a high-performance placement algorithm for large-scale heterogeneous FPGAs with clock constraints. We first propose a connectivity-aware and type-balanced clustering method to construct the hierarchy and improve the scalability. In each hierarchy level, we develop a novel hybrid penalty and augmented Lagrangian method to formulate the heterogeneous and clock-aware placement as a sequence of unconstrained optimization subproblems and adopt the Adam method to solve each unconstrained optimization subproblem. Then, we present a matching-based IP blocks legalization to legalize the RAMs and DSPs, and a multi-stage packing technique is proposed to cluster FFs and LUTs into HCLBs. Finally, history-based legalization is developed to legalize CLBs in an FPGA. Based on the ISPD 2017 clock-aware FPGA placement contest benchmarks, experimental results show that our algorithm achieves the smallest routed wirelength for all the benchmarks among all published works in a reasonable runtime.[SDGs]SDG16conference paper10.1145/3489517.35305672-s2.0-85137455971https://api.elsevier.com/content/abstract/scopus_id/85137455971