黃俊郎臺灣大學：電子工程學研究所林政偉Lin, Chen-WeiChen-WeiLin2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57412薄膜電晶體陣列是一種擁有數千至數百萬個圖素之矩陣結構的電路。若是需要測試所有在陣列上的圖素與傳輸線是否有製造上的缺陷，這將是一件相當困難的工作。因此，傳統上都必須使用大量的探測埠與相當長的測試時間以致於達到夠高之測試的準度。為了改善此情形，在這篇論文中提出了兩個分別針對圖素儲存電荷和掃描線斷裂之內建式自我測試技術。所提出之技術都可被應用在SoG (System on Glass)製造概念。TFT array is a matrix-like structure which contains thousands to millions pixels to display information. However to it’s difficult to make sure that the TFT panel manufactured is no-defect which means all the pixels are well and all the metal wires are continuous. Therefore it’s necessary to test the array including the wires and the pixels. For testing the TFT array, large probes number of ATE and long testing time are needed traditionally. To improve this, this thesis proposed two built-in self-test techniques for testing the pixels and the scan/data line respectively. Both the technique can also be applied into SoG (System on Glass) concept.Abstract...........................................................................................................................i Chapter 1 Introduction...................................................................................................1 1.1 Motivation......................................................................................................1 1.2 Short summary of proposed methods.............................................................3 Chapter 2 Preliminaries..................................................................................................4 2.1 TFT Array Driving Circuitry..........................................................................4 2.1.1 The Scan Driver..................................................................................4 2.1.2 The Data Driver...................................................................................7 2.2 TFT Array Testing.......................................................................................10 2.2.1 Common TFT Array Defects............................................................10 2.2.2 TFT Array Manufacturing Testing Techniques................................12 2.2.3 TFT Array Design-for-Test Techniques.............................................14 2.3 System-on-Glass Design and Test Challenges.............................................16 Chapter 3 A Charge Sensing Technique for TFT Array Testing...................................18 3.1 Overview......................................................................................................18 3.2 The Charge Sensing and Serial Readout Process.........................................20 3.2.1 The Pixel Model...........................................................................20 3.2.2 Functional mode...........................................................................21 3.2.3 Charge Sensing Mode..................................................................22 3.2.4 The serial readout mode...............................................................28 3.2.5 The charge sensing test flow.........................................................30 3.3 Control signal generation.............................................................................32 3.4 Practical issues.............................................................................................33 3.5 Simulation results.........................................................................................34 Chapter 4 A Testing & Repairing Technique for Open Scan Line Defect....................38 4.1 The scan line self-testing and repair scheme................................................38 4.1.1 Scan Line Testing..............................................................................40 4.1.2 Scan Line Repair...............................................................................43 4.2 a-Si Circuit Design.......................................................................................45 4.2.1 Conventional active load inverter......................................................45 4.2.2 The three-stage inverter with positive feedback................................46 4.2.3 One-stage inverter with auto-on/off active load................................48 Chapter 5 Conclusion & Future Work..........................................................................51 5.1 Conclusion....................................................................................................51 5.2 Future work..................................................................................................51 References....................................................................................................................52952660 bytesapplication/pdfen-US薄膜電晶體陣列內建式自我測試電荷感測內建式自我修復TFT arraybuilt-in self-testcharge sensingbuilt-in self-repairthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57412/1/ntu-96-R94943164-1.pdf