Test time reduction in scan designed circuits

Dept. of Electr. Eng., National Taiwan Univ.Lai, Wen-JoungWen-JoungLaiKung, Chen-PinChen-PinKungLin, Chen-ShangChen-ShangLin2007-04-192018-07-062007-04-192018-07-061993-02http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032389application/pdf510772 bytesapplication/pdfen-USTest time reduction in scan designed circuitsjournal article10.1109/EDAC.1993.386427http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032389/1/00386427.pdf