劉致為臺灣大學:電子工程學研究所郭平昇Kuo, Ping-ShengPing-ShengKuo2010-07-142018-07-102010-07-142018-07-102009U0001-1102200923013400http://ntur.lib.ntu.edu.tw//handle/246246/189139本論文中，我們研究矽鍺金氧半元件並且分為實驗部分和模擬部分。 首先，因為矽鍺量子點可以束困電洞，我們首次發現矽鍺量子點的金氧半穿隧二極體會有電洞電流阻礙的現象發生。五層自我生成的矽鍺量子點，每層以一層74奈米的矽為間隔，並在最上方蓋一層130奈米的矽。在結構中加入矽鍺量子點可以在價電帶束困電洞並且形成位障來阻擋電洞電流，實驗發現不管是正偏壓或負偏壓電流都被有效降低。屬-氧化物-N型鍺結構被製作成光偵測器。我們使用鋁和鉑當電極去研究此光偵測器的傳輸機制。在負偏壓時，鋁電極元件的暗電流是由在空乏區內由於熱產生的少數載子和從鋁穿隧到Ｎ型鍺導電帶的電子電流所組成。然而對鉑電極元件而言，由於鉑(5.65電子伏特)相對鋁(4.15電子伏特)具有較高的金屬功函數，所以從金屬穿隧到Ｎ型鍺導電帶的電子電流將被大大的降低。們製作Ｎ型矽/矽鍺/矽量子井的蕭基二極體並利用鉑當電極，我們發現由於矽鍺量子井在價電帶的能帶偏差所引起的電洞累積會縮短空乏區的寬度。在逆偏壓時，空乏區的縮短會增加電容和電流。傳統的電容電壓量測方式不能用來量測矽/矽鍺/矽量子井結構的消基二極體的位障。二部分是模擬，分為應用在動態記憶體上的馬鞍形場效電晶體和矽/鍺/矽量子井結構Ｐ型場效電晶體。由於矽/鍺/矽量子井結構會導致空乏區的縮短，因此不需要額外的摻雜去防止源極和汲極的貫穿。對50奈米以下的動態記憶體而言，馬鞍形場效電晶體比鰭片場效電晶體擁有較低的漏電和較佳的特性，我們提出新結構和改變摻雜方式去降低漏電和閘極電容。In this dissertation, the SiGe metal-insulator-semiconductor devices are studied and we divide into the experiment part and the simulation part.irst, the blockage of hole transport due to excess holes in SiGe dots was observed in the metal-oxide-semiconductor tunneling diodes for the first time. The 5 layers of self-assembled SiGe dots are separated by 74 nm Si spacers and capped with a 130nm Si. The incorporation of SiGe dots confines the excess holes in the valence band, and forms a repulsive barrier to reduce the hole transport current at positive and negative gate biases. A metal/oxide/n-Ge structure has been utilized as a photodetector. We use Al and Pt as the gate electrodes to evaluate the transport mechanism of the MOS detector. At negative gate bias, the dark current of the Al gate detector is composed of the thermal generation of minority carriers in the depletion region and the electron current tunneling from Al to conduction band of the n-type Ge substrate. However, for the Pt gate detector at negative gate bias, the electron tunneling from Pt to conduction band of the n-type Ge is greatly reduced due to the large work function of Pt (5.65 eV) as compared to Al (3.15 eV). he hole confinement due to the valence band offset of the Si/SiGe/Si quantum well causes the shrinkage of depletion region for the n-type Si/SiGe/Si Schottky barrier diodes with Pt gates. The shrinkage of depletion region at reverse bias increases capacitance and current. The conventional capacitor-voltage method can not be used to measure the barrier height of Si/SiGe/Si quantum well Schottky diodes due to the shrinkage of depletion region. The second part is the simulation work of saddle FinFETs for DRAM applications and Si/Ge/Si QW pFETs. No punch-through anti-doping is required for the Si/Ge/Si pFETs due to the shrinkage of depletion region. The saddle FinFETs are demonstrated to be more suitable than the bulk FinFETs for sub-50nm DRAM applications. We proposed new structure and optimized the doping profiles in source/drain to reduce the leakage current and word-line capacitance.List of Figures ΧІІist of Tables ΧVIІІhapter 1 Introduction 1 1.1 Motivation 1 1.2 Planar Bulk-Si MOSFET Scaling Challenges 3 1.3 General Background for Bulk FinFET 4.4 General Background for Ge Quantum Well pFET 6 1.5 Dissertation Organization 8 1.6 Reference 10hapter 2 Transport Mechanism of SiGe Dot MOS Tunneling Diodes 14.1 Introduction 142.2 Device Fabrication 15 .3 LPD Oxide Deposition 17 2.4 Transport mechanisms of Metal-Oxide-Semiconductor Devices 18 2.4.1 Control p-Si 18 2.4.2 SiGe-dot MOS Devices 23 2.4.3 Results of LPD Oxynitride 28 2.4.4 Low Temperature Results 312.5 Conclusion 382.6 Reference 38hapter 3 Dark current reduction of Ge MOS photodetectors by high work function electrodes 3.1 Introduction 43.2 Experiment 44.3 Results and Disscusion 45.4 Conclusion 50.5 References 50hapter 4 Si/Si0.2Ge0.8/Si Quantum Well Schottky Barrier Diodes 52 4.1 Introduction 52 4.2 Transport Mechanism of Schottky Barrier Diodes 53 4.2.1 Current Analysis of Schottky Barrier Diodes 53 4.2.2 Quantum Transmission Coefficient 57 4.2.3 Transport Equation 59 4.2.4 Thermionic-Emission Theory 61 4.2.5 Tunneling Current 65 4.3 Result and Discussions 66 4.3.1 Device Fabrication 66 4.3.2 C-V Characteristics of Schottky Barrier Diodes 67 4.4.3 I-V Characteristics of Schottky Barrier Diodes 72 4.3.4 Photo Response of Schottky Barrier Diodes 74.4 Conclusion 78.5 Reference 78hapter 5 Simulation Study of Ge Quantum Well pFET 81.1 Introduction 81 76.1.1 Advantage of Germanium MOSFETs 81 76.1.2 Issues Of Bulk Ge MOSFET 82 77.2 Device Structure 84.3 Models and Parameters of Simulation 86 81 5.3.1 Si/Ge Band Offset and Band-to-Band Parameter 86 5.3.2 Self-Consistent Schrodinger-Poisson Solution 89.4 Results and Discussion 91.4.1 Substhreshold Slope Modification of pFET 91.4.2 Cap Thickness Variation 94.4.3 Ge layer Thickness Variation 98 5.5 Conclusion 101 5.6 Reference 101hapter 6 Simulation Study of Body-Tied Saddle FinFETs for Sub-50 nm DRAM Generation 104.1 Introduction 104 6.2 Introduction of DRAM 105 112 6.2.1 DRAM Scaling 105 6.2.2 The Reverse Body Bias 107 6.2.3 The Negative Word Line 108 6.3 Model of Band-to-Band Tunneling 109 6.4 Simulation Results and Discussion 113 6.4.1 Device Structure 113 6.4.2 Threshold Voltage Variation with Recess Depth 115 6.4.3 Fin Height and Fin Width Variation 116 6.4.4 DIBL with different Body bias 118 6.4.5 Gate-induced-Drain-Lleakage (GIDL) and junction leakage (JLK) 119 6.4.6 Saddle FinFET v.s bulk FinFET 121 6.4.7 The effect of side gate-to-S/D overlap length 122 6.4.8 Side Wall Oxide 124 6.4.9 Lightly Drain Doping (LDD) 126 6.5 Conclusion 128 6.6 Reference 128hapter 7 Summary and Further Work 132.1 Summary 132 7.2 Further Work 133 138ppendix Related Publication 1364517339 bytesapplication/pdfen-US矽鍺金氧半相斥位障蕭基馬鞍形場效電晶體SiGeMISrepulsive barrierSchottkysaddle FinFETsthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189139/1/ntu-98-D93943030-1.pdf