Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem

Ma, T.-C.T.-C.MaChen, T.-C.T.-C.ChenChen, L.-G.L.-G.ChenLIANG-GEE CHEN2018-09-102018-09-102014http://www.scopus.com/inward/record.url?eid=2-s2.0-84905233716&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/384578[SDGs]SDG7Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystemconference paper10.1109/ICASSP.2014.6854330