呂學士Lu, Shey-Shi臺灣大學:電子工程學研究所方柏翔Fang, Po-HsiangPo-HsiangFang2010-07-142018-07-102010-07-142018-07-102009U0001-2807200917563400http://ntur.lib.ntu.edu.tw//handle/246246/189212As the rapid growth on the development of the wireless communication system, the requirement for the ADC that connect the digital and analog circuits becomes stricter and stricter. In this thesis, two kinds of ADCs are implemented that contain power-saving techniques.n Chapter 3 of this thesis, a low power SAR ADC is presented which uses the advantage of the fully differential structure to decrease the requirement of capacitors, that makes the chip area smaller while get the same resolution as the traditional circuit. The chip is fabricated by TSMC 0.35um 2P4M CMOS technology and the measurement results will be shown. n Chapter 4, a pipelined ADC is introduced which uses opamp current reuse technique to decrease the power dissipation without summing node reset problem. As a result, we can get the advantage of pipelined ADC that has high operation speed without massive power consumption.致謝 i文摘要 iiiBSTRACT ivONTENTS vIST OF FIGURES viiiIST OF TABLES xiihapter 1 Introduction 1hapter 2 The Fundamentals of Analog-to-Digital Converters 3.1 Introduction 3.2.1 Resolution 4.2.2 Offset Error and Gain Error 4.2.3 Differential Nonlinearity （DNL） 5.2.4 Integral Nonlinearity（INL） 6.2.5 Signal-to-Noise Ratio（SNR） 7.2.6 Signal-to-Noise and Distortion Ratio（SNDR） 7.2.7 Effective Number of Bits（ENOB） 7.2.8 Total Harmonic Distortion（THD） 8.2.9 Spurious Free Dynamic Range（SFDR） 8.2.10 Dynamic Range 9.3 ADC Architectures 10.3.1 Flash ADC 10.3.2 Successive Approximation ADC 11.3.3 Pipelined ADC 13.3.4 Delta-Sigma ADC 13hapter 3 A 2.5V, 10-bits, Low Power Successive Approximation ADC for Wireless sensor Network 16.1 Introduction 16.2 SAR ADC circuit design 16.2.1 Basic Operation of Charge-Redistribution SAR ADC 16.2.2 Circuit Implementation of This Design 18.2.3 Building Blocks 21.3 SAR ADC Simulation 35.3.1 The Simulation Techniques 35.3.2 Function Simulation 36.3.3 Static Performance Simulation 36.3.4 Dynamic Performance Simulation 38.4 Measurement Results 39.4.1 The PCB Design 41.4.2 Measurement Setup 42.4.3 Static Performance Measurement 43.4.4 Dynamic Performance Measurement 45.4.5 Performance Metric 49hapter 4 A 3V, 10-bit, 50 MHz Pipelined ADC with OP Current Reuse 50.2.1 Principles of Pipelined ADC 50.2.2 Digital Error Correction Technique 54.2.3 1.5-bit Per Stage Architecture 58.3.1 Speed Requirement 59.3.2 Gain Requirement 61.4.1 Introduction 61.4.2 Operation of OPAMP Sharing 62.5 Pipelined ADC Circuit Implementation 65.5.1 System Architecture of this design 65.5.2 Circuit Design of the Components 66.5.3 Simulation Results of The Proposed Pipelined ADC 90.6.1 The PCB design 92.6.2 Measurement Setup 93.6.3 Static Performance Measurement 94.6.4 Dynamic Performance Measurement 94.6.5 Performance Metric 98hapter 5 Conclusion 99eferences 1007672390 bytesapplication/pdfen-US類比數位轉換器連續漸進式管線式ADCSARpipelinedthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189212/1/ntu-98-R96943050-1.pdf