Dept. of Electr. Eng., National Taiwan Univ.Fang, J.P.J.P.FangTong, Y.-S.Y.-S.TongSAO-JIE CHEN2018-09-102018-09-10200319308868http://www.scopus.com/inward/record.url?eid=2-s2.0-33645748798&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/303243To deal with the floorplan design in a System-on-a-Chip (SOC), we have developed an EDA tool that simultaneuosly considers the problems of routing and buffer-insertion in floorplanning. This routing and buffering tool mainly contains a Manhattan routing (MR) algorithm and a maze-based between-buffer routing (MBR) algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution. © 2003 IEEE.application/pdf314617 bytesapplication/pdfBuffer insertion; Floorptanning; Global routingAlgorithms; Application specific integrated circuits; Buffer circuits; Iterative methods; Programmable logic controllers; System-on-chip; Buffer insertion; Floor-planning; Floorplan design; Floorptanning; Global routing; Manhattan routing; Processing speed; System on a chip; Integrated circuit designconference paper10.1109/VTSA.2003.12525842-s2.0-33645748798