Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model

J. B. KuoS. C. LinJAMES-B KUO2018-09-102018-09-102001-10http://scholars.lib.ntu.edu.tw/handle/123456789/294328Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Modelconference paper10.1109/icsict.2001.9820382-s2.0-84964510380