A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator

Dept. of Electr. Eng., National Taiwan Univ.Liu, Tsung-TeTsung-TeLiuWang, Chorng-KuangChorng-KuangWang2007-04-192018-07-062007-04-192018-07-062004-09http://ntur.lib.ntu.edu.tw//handle/246246/200704191001707application/pdf314405 bytesapplication/pdfen-USA 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generatorjournal article10.1109/ESSCIR.2004.1356696http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001707/1/01356696.pdf