Hwei-Yu LeeI-Hsin WangSHEN-IUAN LIU2018-09-102018-09-102007-09http://scholars.lib.ntu.edu.tw/handle/123456789/333737A 7-bit 400 MS/s sub-ranging flash analog-to-digital data converter (ADC) with short latency is presented. To improve the sampling rate, the fine pre-amplifiers combined with the switched current sources are adopted instead of the switch matrix in a conventional sub-ranging ADC. The proposed architecture avoids the noise coupling from the switches and reduces the parasitic capacitances, which limit the resolution and bandwidth of a sub-ranging ADC. This prototype has been fabricated in 0.18um CMOS process. It dissipates 108 mW with a supply of 1.8 V and occupies the active area 0.64mm 2 . The measured performance achieves the signal to noise plus distortion ratio (SNDR) of 40 dB at sampling rate of 400 MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.9-LSB and ±0.7-LSB, respectively.[SDGs]SDG7conference paper10.1109/SOCC.2007.45454152-s2.0-51049123804