以寬頻縮小化電磁能隙結構抑制系統構裝兆赫茲雜訊研究

2011-08-012024-05-17https://scholars.lib.ntu.edu.tw/handle/123456789/691409摘要：數位電路在高元件密度、高時脈速度與微小化體積發展趨勢下，系統整合封裝 (System in Package, SiP)的設計將成為未來的主軸。在高功率與低電壓準位的架構下，電 路抗雜訊的干擾的能力已嚴重降低。數位電路同步切換時的暫態電流將產生同步切換雜訊(Simultaneous Switching Noise, SSN)、或是接地彈跳雜訊(Ground Bounce Noise, GBN)，當其在電源/接地層間傳播，將造成信號完整度、電磁干擾的問題，因此，保持電源完整度之重要性與日俱增。最新的解決方案是在電源/接地層使用電磁能隙結構 (Electromagnetic Bandgap Structure, EBG)，EBG 能產生禁止帶並有效的抑制GBN。本計畫將進行寬頻、縮小化、低成本之EBG 的研究與設計，也進行分析與驗證GBN 對SiP 上射頻電路(Radio Frequency Integrated Circuit, RFIC)輸出信號的影響，藉此強調晶片與封裝共同設計的重要性。在第一年的子計劃，我們利用接地平面擾動晶格(Ground Surface Perturbation Lattice, GSPL)結構取代光子晶體電源層板(Photonic Crystal Power Layer, PCPL)中的高介電係數 材料圓柱，並建立其等效電路模型與模擬、量測結果比對。在第二年子計劃中，我們將提出多連通柱接地晶格(Multiple Via Ground Surface Perturbation Lattices, MV-GSPL)，利 用GSPL 進一步的增加LPC-EBG 的頻寬以及降低操作頻率而不需放大其尺寸，並發展其低、高頻截止頻率公式以方便設計。最後一年的子計劃中，則是建立系統封裝與射頻晶片共模擬的方法並驗證其正確性。我們將進行製作包含射頻電路(本計劃中為LNA) 的SiP，以模擬與量測的角度說明GBN 對SiP 上射頻電路輸出信號的影響。並且製作內埋EBG 電源/接地層板的封裝驗證利用EBG 電源/接地層將能有效地抑制雜訊並確保射頻電路的輸出信號的完整度。<br> Abstract: While the operating voltage is decreasing and consumed power increasing, the performance of circuits would easily been affected or degraded by aggressive electromagnetic noise. Because of the data rate of circuit is up to GHz, the non-ideal effect on power distributed network (PDN) due to the physical structures can no longer be neglected. Among these non-ideal effects, parasitic inductance is the most important part. When the digital circuit is operating, the transient current on power/ground pairs goes through these parasitic inductances would induce simultaneous switching noise (SSN), or ground bounce noise (GBN). This noise will propagate between power/ground planes and causes some electromagnetic problems to degrade the output signal, we call it power integrity (PI) problem. To obtain good performance, circuit design with concurrently considering PI issues has become essential. Several works have contributed to reduce the GHz noise. Using embedded periodic structure, such as Electromagnetic bandgap (EBG), between power/ ground planes to suppress the GBN is a novel idea. The EBG structure can provide wide stop-band and reduce the in-band noise effectively. However, applying EBG structure on practical SiP circuit has not yet been seen due to the inherent large size of the conventional EBG structure. In this project, we will propose a novel EBG structure with emphasis on miniaturization, wider bandgap, and lower cost. The influence of GBN to the behavior of RFIC (an LNA in this project) in a SiP can be reduced through the developed miniaturized EBG structure. It will be shown through chip-PKG co-simulation and measurement. In the first-year subproject, a low-cost structure called ground surface perturbation lattice (GSPL) will be used to replace the high dielectric constant material rods of the photonic crystal power layer (PCPL). We will analyze this structure by deriving and constructing the equivalent circuit model. The result of co-simulation, equivalent model, and measurement will be compared and our design concept would be validated. In the second-year subproject, we will propose a new-type EBG using Multiple Via Ground Surface Perturbation Lattices (MV-GSPL) to enhance the bandwidth and miniaturize the size of the long period coplanar electromagnetic bandgap (LPC-EBG) power/ground layers. The formula for the lower and upper sideband cut-off frequency of MV-GSPL will be developed to make our design efficient. In the third year subproject, a methodology of co-simulation including the SiP and RFIC (an LNA) will be built up and its accuracy will be authenticated. The result of degraded output signal of LNA due to GBN and the improvement by implementing our EBG structure can be both observed obviously in both chip-package-PCB co-simulation and measurement. The better PI performance of circuits can be obtained by employing the developed BG structure in RF-SiP.以寬頻縮小化電磁能隙結構抑制系統構裝兆赫茲雜訊研究