楊佳玲Yang, Chia-Lin臺灣大學:資訊工程學研究所陳彥名Chen, Yen-MingYen-MingChen2010-05-182018-07-052010-05-182018-07-052008U0001-2608200819221600http://ntur.lib.ntu.edu.tw//handle/246246/183660隨著製程進步，如何減少漏電(leakage)的問題將會更加嚴苛。在以往圖形處理器(GPU)的設計方面，主要都著重在動態耗電(dynamic power)方面的問題，以動態調整電壓及頻率(DVFS)以及時脈閘控(clock-gating)為主要的策略。在這篇論文中，我們使用電源閘控(power-gating)來減少漏電，電源閘控是將正在閒置的處理單元(functional unit)整個關掉來節省漏電。因為遊戲中場景的變化加上畫面更新頻率(frame rate)的目標，在每個畫面(frame)所需要的著色處理器(shader)資源數也會不一樣，因此我們設計一個歷史基準(history-based)的預測器來預測每個畫面所需要的圖形處理器資源數，藉此有機會將多餘的圖形處理器關掉以節省漏電。們的實驗結果呈現出透過我們的電源閘控策略，最多可以節省到15.2%的漏電，而關閉些許圖形處理器所造成的效能下降非常有限。As the technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low power GPU (Graphics Processing Unit) focuses techniques for dynamic power reduction, such as DVFS(Dynamic Voltage/Frequency Scaling), and clock gating. In this paper, we explore the potential of adopting architecture-level power-gating technique to reduce leakage power of GPU. Power-gating is to turn off a functional unit during its idle period. Due to different scene complexity, the required shader resources to achieve target frame rate varies among frames. Therefore, we adopt a history-based approach to predict required shader resources in a frame, and turn off redundant shader processors.he experimental results show that the proposed power-gating strategies achieve significant leakage reduction with negligible performance degradation. To achieve longer execution time and better energy utilization, power management is becoming more and more important issue to both batterypowered devices and tethered equipments. As CMOS technology evolving, leakage power will be the dominant source of power dissipation. In this paper, we explore possible redundant shader resources in modern GPU with unified shader architecture from exploiting power-gating perspective. We demonstrate observed redundant shader units from Frame-Level, which could be power-gated further to save leakage. In Frame-Level, we show that under unified shader architecture, there still exists redundant shader processors due to imbalance workload among frames. By deciding number of active shader processors dynamically using simple history-based prediction, we show that maximum of 15.2% shader leakage power could be saved while meeting performance requirement.Abstract i Introduction 1.1 Overview of this Thesis 3.2 Organization of this Thesis 4 Related Works 5 Analysis of Power-Gating Opportunity 11.1 Overview of GPU with Unified Shader Architecture 11.2 Variation of Shader Computation in Frame-Level 15.3 Workload Variation in Frame-Level 18.4 Potential Energy Saving 21 Applying Power-gating Techniques in Frame-Level 24.1 Frame-Level: Shader Shutdown Technique 24.2 Implementation of Shader Shutdown Technique 26 Experimental Setup and Results 27.1 Simulation Environment 27.2 Trace Files 28.3 Results 29 Conclusion 32ibliography 33application/pdf1548206 bytesapplication/pdfen-US圖形處理器電源閘控漏電GPUPower-GatingLeakage[SDGs]SDG7thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/183660/1/ntu-97-R95922125-1.pdf