陳少傑臺灣大學:電子工程學研究所劉淑敏Liu, Shu-MinShu-MinLiu2010-07-142018-07-102010-07-142018-07-102009U0001-1708200915580900http://ntur.lib.ntu.edu.tw//handle/246246/189154快速傅利葉轉換處理器一直為影像處理以及通訊系統所廣泛使用，截至目前為止每年仍有許多關於快速傅利葉轉換處理器的研究不斷地進行與發表，意味著對於提升快速傅利葉轉換處理器各方面功能之需求不曾中斷，因此如何增進效能以及減少硬體資源為快速傅利葉轉換處理器的最大課題。於快速傅利葉轉換運算後的結果為位元反向順序的輸出序列，這並不適合用於快速傅利葉轉換的一些應用如正交分頻多工系統，本論文提出了一種節省記憶體快速傅利葉轉換處理器的新式架構與設計方法，能夠不需經由額外的位元翻轉(bit-reversed)電路亦可產生最佳輸出資料之順序，此架構對於那些要求快速傅利葉轉換器處理連續輸入的資料序列循序輸出的系統來說，是非常合適的設計架構。Fast Fourier transform (FFT) processors have been widely used in image processing as well as in communication systems. Up to date, many researches about FFT are being carried on and unceasingly got published every year. It signifies that the demand on how to improve the computation speed never stop. Also, trade-off between the performance and hardware resources of an FFT design becomes an important issue. typical FFT operation transforms an in-order input sequence into an output sequence in bit reverse order, which is not suitable to use in some application like orthogonal frequency division multiplexing (OFDM). This work proposed a novel memory-based FFT architecture which has the property that both inputs and outputs are addressed in natural order without a bit-reversed electric circuit. It is very suitable for those systems where the continuous data sequences that call for the FFT processing enter and exit from the system sample by sample sequentially.ABSTRACT iIST OF FIGURES vHAPTER 1 INTRODUCTION 1.1 Orthogonal Frequency Division Multiplexing 1.2 Fast Fourier Transform in OFDM Systems 3.3 Fast Fourier Transform Algorithm 4.3.1 Decimation in Time FFT Algorithms 6.3.2 Decimation in Frequency FFT Algorithms 8.3.3 Radix-4 Algorithms 10.4 Thesis Organization 11HAPTER 2 BACKGROUND INFORMATION 13.1 Memory-Based FFT Architecture 13.2 Pipelined FFT Architecture 14.2.1 Single-Path Delay Feedback (SDF) Architecture 14.2.2 Multiple-Path Delay Commutator (MDC) Architecture 16.3 Cache Memory FFT Architecture 17.4 Array FFT Architecture 18.5 Summary 18HAPTER 3 MEMORY-BASED FFT ARCHITECTURE EVOLUTION 19.1 Type I of Memory-Based FFT Architecture 19.1.1 Phase Analysis 21.1.2 Utilization Analysis 22.2 Type II of Memory-Based FFT Architecture 23.2.1 Phase Analysis 24.2.2 Utilization Analysis 26.3 Type III of Memory-Based FFT Architecture 26.3.1 Phase Analysis 27.3.2 Utilization Analysis 28.4 Type IV of Memory-Based FFT Architecture 28.4.1 Phase Analysis 29.4.2 Utilization Analysis 30.5 Summary 30HAPTER 4 A NOVEL FFT DESIGN AND EXPERIMENTAL RESULTS 31.1 Considering the Reorder Buffer 32.2 Memory Address Mapping Improvement 34.3 A Novel FFT Architecture 35.3.1 Phase Analysis 37.3.2 Timing 38.3.3 Utilization Analysis 39.3.4 Waveform 39.3.5 Layout View 41.4 Parallel Architecture with Two PEs 42.4.1 Layout View 44.5 Parallel Architecture with Four PEs 45.5.1 Layout View 46.6 Other Implementation 47.7 Summary 48HAPTER 5 CONCLUSION 53EFERENCES 55518202 bytesapplication/pdfen-US傅立葉記憶體架構Memory-basedFFTthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189154/1/ntu-98-P96943002-1.pdf