Design and test of memory management unit and cache controller chip

Dept. of Electr. Eng., National Taiwan Univ.Hsieh, DavidDavidHsiehLai, Fei-peiFei-peiLai2007-04-192018-07-062007-04-192018-07-061993-10http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032360application/pdf335995 bytesapplication/pdfen-USDesign and test of memory management unit and cache controller chipjournal article10.1109/TENCON.1993.319916http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032360/1/00319916.pdf