Yu, T.-B.T.-B.YuHEN-WAI TSAOSHEN-IUAN LIU2018-09-102018-09-102001http://www.scopus.com/inward/record.url?eid=2-s2.0-0035360494&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/292343A direct digital frequency synthesiser using a new decomposition method without the large sine ROM table is presented. To improve its operating frequency a pipeline structure has been utilised. It has been fabricated in a 0.6μm single-poly double-metal (SPDM) CMOS process and its core area is 0.95 × 1.1mm2. The maximum operating frequency is 85 MHz. For a 10MHz sinusoidal output, the phase noise is -114dBc/Hz at an offset frequency of 10kHz. The measured SNR is 60.77dB and worst case spurious is -67.6dBc. Its power dissipation is 80mW at 80MHz under the 5V supply.[SDGs]SDG7CMOS integrated circuits; Phase locked loops; Pipeline processing systems; ROM; Signal to noise ratio; Single mode fibers; Spurious signal noise; Wireless telecommunication systems; Pipeline direct digital frequency synthesizers; Frequency synthesizersjournal article10.1049/ip-cds:200101582-s2.0-0035360494