Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces

H.-H. ChuangC.-J. HsuM.-Z. HongD. HsuR. HuangL.-C. HsiaoTZONG-LIN WU2018-09-102018-09-102009-12http://scholars.lib.ntu.edu.tw/handle/123456789/352245[SDGs]SDG7Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfacesconference paper10.1109/EDAPS.2009.54040142-s2.0-77950225741