Chi-Nan ChuangSHEN-IUAN LIU2018-09-102018-09-102008-1015497747http://scholars.lib.ntu.edu.tw/handle/123456789/342653https://www.scopus.com/inward/record.uri?eid=2-s2.0-57949115351&doi=10.1109%2fTCSII.2008.2002561&partnerID=40&md5=1e067166a2423e3148db9d9d1a3254b0A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%. © 2008 IEEE.Calibration; Cycle jitter; Delay-locked loop (DLL); Duty cycle correction; Edge combinerCalibration; Jitter; Voltage dividers; 90-nm cmos; Delay-locked loops; Duty cycle correction; Edge combiners; Operation frequency; Peak-to-peak; Supply voltages; Voltage-controlled delay lines; Delay lock loopsjournal article10.1109/TCSII.2008.2002561