李泰成臺灣大學：電子工程學研究所陳平Chen, PingPingChen2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57414近年來光通訊網路的資料傳輸速率急速成長，使得實體層介面上的電路設計遇到相當大的挑戰。過去光纖常被視為完美的傳輸通道，但隨著資料速率達到每秒十億位元以上，碼際干擾逐漸成為數位通信上非常重要的一個課題－它限制了光纖上的傳輸速率以及傳輸距離。 運用光學上的技術亦可補償光纖的非理想性，其優勢在於不需要高速電路，然而從電路領域出發的補償有較高的彈性以及較低的成本，因此咸認是較佳的選擇。在電路補償方面，可以使用數位或類比的等化器。與類比等化相比，數位等化擁有比較精確的表現，但以數位方式實現等化器在高速類比╱數位轉換器的製作上有著很大的瓶頸。數位等化所需的大面積、高功率消耗使純類比的等化器成為一個更有效率的解決方案。 在各種百億位元乙太網路（IEEE 802.3ae）的子規格中，10GBASE-LX4特別引起我們的注意。它的低成本特性在短距離的應用中擁有非常大的經濟優勢，例如使用在區域網路上。10GBASE-LX4採用分波多工技術以及8B/10B編碼系統，因此其資料傳輸速率為每秒3.125十億位元。 在本論文中，我們設計了一個適用於10GBASE-LX4系統的四級、部分延遲間隔類比有限脈衝響應濾波器做為通道等化器。其中的連續時間延遲線是以電感電容梯狀網路實現，它提供了線性及寬頻特性。電路實作上使用標準0.18微米互補金氧半導體製程，所設計的類比等化器可以成功地回復經由多模光纖傳輸之每秒3.125十億位元的隨機信號；在1.8伏電源供應下，功率消耗為2.3毫瓦。此外，我們還設計了一個操作在1.5625十億赫茲的延遲鎖定迴路，用以鎖定有限脈衝響應濾波器中延遲線的延遲時間。兩個電路的晶片面積分別為1.77 × 0.64毫米平方以及1.12 × 0.99毫米平方。The exploring increasing of data rate in optical networks in recent years has created a major challenge for electronic circuits used at the interface of the optical physical layer links. Historically, the optical fiber used to be considered as a perfect channel. However, as the data rate increases above Gb/s, intersymbol interference (ISI) becomes an essential issue in digital communications, limiting the achievable transmission speed and distance over fibers. Optical techniques can be used to compensate the impairments of optical fibers, with the advantage of requiring no high-speed electronic circuits. Nevertheless, electronic compensation is more flexible and economical, and may be a better choice. As to electronic compensation, digital or analog equalizers can be used. Digital (DSP based) equalization offers more accurate and higher performance comparing with analog counterpart. But the design of digital equalization has a bottleneck on the implementation of high-speed ADCs, which need large area and high power consumption. Consequently, pure analog equalizer is a more efficient solution. Among different sub-standards of 10 Gigabit Ethernet (IEEE 802.3ae), 10GBASE-LX4 particularly attracts us. Its low-cost property has a substantially economical advantage on short-haul applications such as LANs. The use of WDM and 8B/10B coding scheme on 10GBASE-LX4 leads to a data rate of 3.125 Gb/s. In this thesis, a 4-tap fractionally spaced analog FIR filter designed for 10GBASE-LX4 fiber-optic communication performs channel equalization. The continuous-time tap delay line is realized by a lumped LC ladder, providing linear and wideband characteristics. Fabricated in a standard 0.18-μm CMOS technology, the analog equalizer can successfully recover the 3.125- Gb/s random data transmitted over MMF channels while dissipating 2.3 mW from a 1.8-V power supply. Furthermore, an additional DLL is proposed to lock the tap delay time of the FIR filter, operating at 1.5625 GHz. The die sizes of two prototypes are 1.77 × 0.64 mm2 and 1.12 × 0.99 mm2, respectively.Chapter 1 Introduction 1 1.1　Motivation and Research Goals 1 1.2　Thesis Overview 2 Chapter 2 Basic Concepts and System Overview 3 2.1　Basic Concepts 3 2.1.1　Random Binary Sequence 3 2.1.2　Eye Diagram 4 2.1.3　Bit Error Rate 7 2.2　Optical Fibers 8 2.2.1　Multi-Mode Fiber 9 2.2.2　Single-Mode Fiber 9 2.2.3　Fiber Dispersion 10 2.2.4　Fiber Losses 12 2.3　Fiber-Optic Communication Systems 13 2.4　10 Gigabit Ethernet 14 2.4.1　Physical Layers of 10 Gigabit Ethernet 14 2.4.2　10GBASE-LX4 15 Chapter 3　System Architecture of a 3.125-Gb/s Analog Equalizer for 10GBASE-LX4 19 3.1　Introduction 19 3.1.1　Equalizer 19 3.1.2　Analog Equalizer 20 3.2　Architecture of Analog Equalizer 22 3.2.1　Traditional Analog Filter Equalizer 22 3.2.2　Analog FIR Filter Equalizer 24 3.3　Channel Model 26 3.4　Behavioral Simulation of a 3.125-Gb/s Analog Equalizer 28 Chapter 4　Implementation of a 3.125-Gb/s Analog Equalizer for 10GBASE-LX4 33 4.1　Architecture 33 4.2　Delay Line 34 4.2.1　Typical Delay Cell 34 4.2.2　Low-Pass Filter Type Delay Cell 35 4.2.3　Lumped LC Ladder Transmission Line 37 4.3　Monolithic Inductor and Varactor 39 4.3.1　Stacked Spiral Inductor 39 4.3.2　MOS Varactor 42 4.3.3　Delay Line Simulation 43 4.4　Analog Multiplier and Output Buffer 45 4.5　Transistor-Level Simulation of Analog Equalizer 46 4.6　Layout and Performance Summary 49 Chapter 5　A High-Speed Delay-Locked Loop with Lumped LC Ladder Delay Line 51 5.1　Introduction 51 5.1.1　DLL in Analog Equalizer 51 5.1.2　DLL Basics 51 5.1.3　Specification of Designed DLL 54 5.2　Circuit Implementation 54 5.2.1　Phase Detector 54 5.2.2　Voltage-to-Current Converter 56 5.2.3　Voltage-Controlled Delay Line 57 5.2.4　Closed-Loop Simulation 58 5.3　Layout and Performance Summary 58 Chapter 6　Conclusions and Further Discussions 61 6.1　Conclusions 61 6.2　Further Discussions 61 6.2.1　Nonidealities of FIR filter 61 6.2.2　TIA Effect 63 6.2.3　Mixed-Signal Equalizer 63 Appendix　Testing Strategies 65 A.1　Testing Strategy of DLL 65 A.2　Testing Strategy of Analog Equalizer 67 Bibliography 68en-US類比等化器有限脈衝響應濾波器光纖通訊延遲鎖定迴路百億位元乙太網路Delay-Locked LoopAnalog EqualizerFiber-Optic CommunicationFIR Filter10 Gigabit Ethernetthesis