A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit

Dept. of Electr. Eng., National Taiwan Univ.Su, K.W.K.W.SuLou, J.H.J.H.LouKuoJB2007-04-192018-07-062007-04-192018-07-061994-06https://www.scopus.com/inward/record.uri?eid=2-s2.0-0029359884&doi=10.1109%2f4.400440&partnerID=40&md5=3e52c996358ab5c29a709bc211e3f69bThis brief presents a BiCMOS dynamic multiplier, which is free from race- and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8 × 8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one. © 1995 IEEEapplication/pdf341156 bytesapplication/pdfen-USAdders; Bipolar transistors; Capacitance; CMOS integrated circuits; Electric power supplies to apparatus; Integrated circuit manufacture; Logic circuits; Logic gates; BiCMOS dynamic logic circuit; BiCMOS dynamic multiplier; Carry look ahead circuit; Charge sharing; Wallace tree reduction architecture; Multiplying circuitsA BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuitjournal article10.1109/ISCAS.1994.4092622-s2.0-0029359884http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032466/1/00409262.pdf