劉致為臺灣大學：電機工程學研究所葉家宏YE, JIA-HONGJIA-HONGYE2007-11-262018-07-062007-11-262018-07-062007http://ntur.lib.ntu.edu.tw//handle/246246/53159目前低溫複晶矽薄膜電晶體仍有需多問題需要解決，如漏電流的問題，以及我們對於複晶矽還有許多物理特性並不是十分的了解，而我們的研究方向就是低溫複晶矽薄膜電晶體之偏壓溫度不穩定性，這是屬於元件可靠度分析的範疇。在我們的論文裡，我們使用了不同的閘極偏壓，配合上不同的溫度以及不同的施以偏壓時間，其中包含了長時間與短時間，去做我們的元件偏壓溫度不穩定性實驗。藉由外在條件的不同，我們去觀察元件之後特性的變化。除了我們將試著去了解低溫複晶矽薄膜電晶體之電性之外，我們也閱讀相關的論文或研究報告，從這些已知的研究之中，尋找可能的發現原因，以及其內部的物理機制為何。基本上我們希望不僅能夠控制變因，明白什麼將會影響什麼，確實做到加速元件劣化的實驗，也就是能夠做到定性的實驗，更進一步，我們更希望能夠做到定量化的實驗，去確實明白產生了什麼改變如氧化層的缺陷增加、界面缺陷的產生，而這些增加的量又為多少。以上的這些，就是我們希望藉由實驗建立相關元件劣化的模型，而這些模型將可以提供如研究電路方面人員的參考。Our thesis studies about bias temperature instability of low temperature polycrystalline silicon thin film transistors. In this thesis, we use different gate bias, stress gate bias time, temperature, and device structures to do our experiment. The different device structures are like LDD, channel types, gate stacks, and different width lengths etc. The goal of our experiment is to understand the electrical property of low temperature polycrystalline silicon thin film transistors. The electrical properties are like humps, threshold voltage shift, on current degrade and leakage current etc. Moreover, we want to build models of low temperature polycrystalline silicon thin film transistors about electrical properties. These models will be help for engineers who work about circuits.Contents List of Figures ………………………………………..VII List of Tables …………………………………………XII Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Thesis Organization 2 Chapter 2 Negative Bias Temperature Instability of LTPS Thin Film Transistor 4 2.1 Introduction 4 2.2 Some Thin Film Transistor Device Physics 6 2.3 NBTI Effect 7 2.4 Experiment Procedure 9 2.4.1 Device Manufacture 9 2.4.2 Experiment Steps 10 2.5 Experiment conclusion 11 2.5.1 The Degradation of Device Parameters after NBTI Stress 11 2.5.2 The On Current Degrade 12 2.5.3 Power Law 13 2.5.4 Delta Threshold Voltage and the Gate Voltage Stress 15 2.5.5 Active Energy of NBTI 16 2.5.6 Leakage Current of NBTI 17 2.6 Negative Bias Temperature Instability of p-channel LTPS TFT Model 18 2.6.1 R-D Model Possible Electrical Chemical Reaction Formula for Our Experiment 18 2.6.2 Generally Reaction-Diffusion Model for NBTI 18 2.6.3 Solution of Reaction-Diffusion-H 20 2.6.4 Another Types of Hydrogen Species 21 2.6.5 Summary 26 2.7 Grain Boundary Theory 28 2.7.1 Seto’s Assumption 28 2.7.2 Doping Types of Poly-silicon 29 2.7.3 Inversion Layer Channel Thickness 30 2.7.4 The Barrier Height of Grain Boundary for Partial Depletion 31 2.7.5 The Barrier Height of Grain Boundary and Gate Voltage and Doping Concentration Relation 32 2.7.6 Levinson method 34 2.8 Summary 37 Chapter 3 Negative Bias Temperature Instability of N-channel LTPS Thin Film Transistor 39 3.1 Introduction 39 3.2 Experiment Procedure 39 3.2.1 Device Manufacture 39 3.2.2 Compare Single and Dual Layer Oxide in N-channel LTPS TFT for NBTI 40 3.2.3 Compare LDD and no LDD structure in n-channel LTPS TFT for NBTI 41 3.2.4 Compare Different Gate Width Lengths in N-channel LTPS TFT for NBTI 42 3.2.5 Compare Different Channel Types of LTPS TFT for Hump 44 3.2.6 The Different Device-Compare Single and Dual Layer Oxide in N-channel LTPS TFT for NBTI 45 3.2.7 The reason to use the same device to experiment 47 3.3 Result and Discussion 47 3.3.1 Compare Single and Dual Layer Oxide in N-channel LTPS TFT for NBTI 47 3.3.2 Compare LDD and No LDD Structure in N-channel LTPS TFT for NBTI 52 3.3.3 Compare Different Gate Width Length in N-channel LTPS TFT for NBTI 58 3.3.4 Compare Different Channel Types of LTPS TFT for Hump 66 3.3.5 The Different Devices-Compare Single and Dual Layer Oxide in N-channel LTPS TFT for NBTI 73 3.4 Negative Bias Temperature Instability of N-channel LTPS TFT Model 76 3.5 Summary 77 Chapter 4 Positive Bias Temperature Instability of N-channel LTPS Thin Film Transistor 82 4.1 Introduction 82 4.2 Experiment Procedure 83 4.2.1 Manufacture 83 4.2.2 Compare Single and dual layer oxide in n-channel LTPS TFT for PBTI 83 4.2.3 The Dual Layer Oxide in N-channel LTPS TFT for PBTI in Long Time 84 4.2.4 The Leakage Current and Drain Voltage 85 4.2.5 The Different Device-The Leakage Current and Drain Voltage 86 4.2.6 The reason to use the same device to experiment 88 4.3 Result and Discussion 89 4.3.1 Compare Single and dual layer oxide in n-channel LTPS TFT for PBTI 89 4.3.2 The Dual Layer Oxide in N-channel LTPS TFT for PBTI in Long Time 95 4.3.3 The Leakage Current and Drain Voltage 98 4.3.4 The Different Device-The Leakage Current and Drain Voltage 103 4.4 Positive Bias Temperature Instability of N-channel LTPS TFT Model and Bias Temperature Instability of N-channel LTPS TFT Leakage Current Model 107 4.5 Summary 110 Chapter 5 Summary 113 5.1 Summary 113 5.2 Future Work 1182788487 bytesapplication/pdfen-US偏壓不穩定性低溫複晶矽薄膜電晶體BTILTPS TFTthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53159/1/ntu-96-J94921020-1.pdf