Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously

S. C. LinJAMES-B KUO2018-09-102018-09-102002-11https://www.scopus.com/inward/record.uri?eid=2-s2.0-0036867036&doi=10.1109%2fTED.2002.804728&partnerID=40&md5=218e579e3ce3377a82a49bbcd1c39070This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT.Compact model; Complementary metal-oxide-semiconductor (CMOS); Partially depleted (PD); PD breakdown voltage; Silicon-on-insulator (SOI); SPICE[SDGs]SDG7Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneouslyjournal article10.1109/TED.2002.8047282-s2.0-0036867036WOS:000179694200023