Che-Fu LiangSy-Chyuan HwuSHEN-IUAN LIU2018-09-102018-09-102007-0409168524http://scholars.lib.ntu.edu.tw/handle/123456789/333716https://www.scopus.com/inward/record.uri?eid=2-s2.0-34247102777&doi=10.1093%2fietele%2fe90-c.4.802&partnerID=40&md5=aa1635c00a74dc1c97025b0b66e7b61bA multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 μm CMOS process. Its active area is 0.41 mm2 and consumes 70 mW including I/O buffers from a 1.8 V supply. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.Burst-mode; Clock and data recovery; Multi-band; Voltage-controlled oscillatorBandwidth; Data reduction; Fiber optic networks; Jitter; Oscillators (electronic); Voltage control; Clock and data recovery; Gated voltage-controlled oscillator (GVCO); Voltage-controlled oscillators; Frequency dividing circuitsjournal article10.1093/ietele/e90-c.4.8022-s2.0-34247102777WOS:000245929000021