臺灣大學: 電信工程學研究所江簡富余超塵Yui, Chau-ChanChau-ChanYui2013-03-272018-07-052013-03-272018-07-052012http://ntur.lib.ntu.edu.tw//handle/246246/253334本論文運用主動式電感、差動主動式電感以及主動式平衡非平衡轉換器在低雜訊放大器與功率放大器晶片設計上。 其一為運用主動式電感於超寬頻低雜訊放大器上，其中主動式電感架構包含一組疊接電晶體及一回授電阻來提昇操作頻率，並在回授路徑上加入共汲極放大器來提高電感 Q 值。實現之晶片面積為 840μm × 610μm，模擬增益在操作頻寬 (3.1-10.3 GHz) 內為 13.68 dB，輸入及輸出反射參數皆小於-10 dB，功耗為 14.02 mW。 其二為運用差動主動式電感之 5 GHz 差動低雜訊放大器，該差動主動式電感使得晶片面積縮小為 750μm × 600μm，模擬增益在操作頻率為 12.5 dB，雜訊指數為 2.7 dB，輸入及輸出反射參數皆小於-10 dB，功耗為 14.2 mW。 其三為運用主動式平衡非平衡轉換器實現之單端輸出功率放大器。與被動式平衡非平衡轉換器相比，其面積縮小許多。全晶片面積為 850μm × 650μm，模擬輸出P1dB在操作頻率 5 GHz 為 13.1 dBm，增益為 26.25 dB，PAE 為 27.9%。An ultra-wideband low-noise amplifier with active inductor is designed and implemented in a TSMC 0.18μm CMOS technology. This active inductor consists of a cascode FET with a feedback resistor, and operates at a high self-resonance frequency. The common-drain FET in the feedback loop enhanced the Q factor of the inductor. The core chip size is only 840 μm × 610 μm. The simulated power gain is 13.68 dB, with the 3-dB bandwidth of 3.1-10.3 GHz. Both the input and ouptut reflection coefficients are less than −10 dB over the entire band. The power consumption, without an output buffer, at 1.8-V supply is 14.016 mW. A differential low-noise amplifier at 5 GHz is designed and implemented in a TSMC 0.18μm CMOS technology. The chip size is reduced by using a pair of differential active inductors with enhanced Q factor and high resonant frequency. The core chip area of this LNA is 0.45 mm2, the simulated power gain is 12.5 dB, the noise figure is 2.7 dB. Both the input and ouptut reflection coefficients are below −10 dB over the entire band, and the power consumption is 14.2 mW. A CMOS single-ended power amplifier with an active input balun is designed and implei mented in a TSMC 0.18μm CMOS technology, which can be implemented in a smaller chip compared with conventional balanced or differential power amplifiers with a passive output balun or off-chip transformer. The proposed power amplifier is fabricated using a TSMC 0.18 μm CMOS process. Its chip size is 0.85 μm × 0.65 μm, the output P1dB is 13.1 dBm, its gain is 26.25 dB, and its PAE of 27.9 %.140 bytestext/htmlen-US主動式電感主動式平衡非平衡式轉換器低雜訊放大器功率放大器超寬頻系統active inductoractive balunLNAPAUWBthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/253334/1/index.html