指導教授：李泰成臺灣大學：電子工程學研究所黃博煌Huang, Po-HuangPo-HuangHuang2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263873本論文提出一個輔以動態元件匹配的連續漸進式類比數位轉換器。 使用此方法可以提升參考數位類比轉換器的線性度，進而降低其面積以及功率消耗。本晶片使用台積電四十奈米低功耗製程實現。在一億六千萬的取樣頻率下，訊號雜訊失真比約為58.01分貝以及訊號無雜散比約為73.59分貝。最大的DNL約為0.66/-0.51 LSB，最大的INL約為0.57/-0.61 LSB。整體電路核心的面積約為0.012平方毫米，在1.1伏特的電源供應下消耗功率約為1.64毫瓦，每次轉換所需要的能量為15.83 fJ。This thesis presents a successive-approximation ADC with dynamic element matching (DEM) technique. It can enhance the linearity of the reference DAC and thus reduce the area and power dissipation of the DAC. This prototype is fabricated in TSMC 40-nm LP 1P6M CMOS technology. It achieves an SNDR of 58.01 dB and an SFDR of 73.59 dB at 160MS/s. The maximum DNL is 0.66/-0.51 LSB and the maximum INL is 0.57/-0.61 LSB. The total active area occupies 0.012 mm2, and the ADC consumes 1.64 mW from a 1.1-V supply. The figure-of-merit (FOM) is 15.83 fJ/conversion-step.摘要 i Abstract ii Contents iii List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Successive-Approximation ADCs 3 2.1 Introduction 3 2.2 ADC Performance Metrics 3 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 3 2.2.2 Signal-to-Noise Ratio (SNR) 6 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 7 2.2.4 Effective Number-of-Bits (ENOB) 8 2.2.5 Spurious-Free Dynamic Range (SFDR) 8 2.2.6 Figure of Merit (FoM) 9 2.3 Introduction to Successive Approximation ADCs 9 2.4 Prior Arts 11 Chapter 3 DAC with Dynamic Element Matching 13 3.1 Introduction 13 3.2 Proposed DAC Architecture 13 3.2.1 Random Rotational Dynamic Element Matching 14 3.2.2 DAC Early Reset 16 3.3 Linearity Analysis of Capacitive DACs 19 3.3.1 Monotonic Switching Binary-weighted DAC 19 3.3.2 Binary-weighted DAC with Early Reset 22 3.3.3 Binary-weighted DAC with DAC early reset and DEM 25 3.4 Simulation of Successive Approximation ADCs 27 3.4.1 Static Performance 27 3.4.2 Dynamic Performance 28 3.4.1 Comparison 32 3.5 Summary 33 Chapter 4 Circuit Implementation of Successive Approximation ADC 35 4.1 Introduction 35 4.2 Analog Building Blocks 35 4.2.1 Sample-and-Hold Circuit 35 4.2.2 Dynamic Comparator 37 4.2.3 Capacitive DAC Array 38 4.3 Digital Building Blocks 38 4.3.1 Comparator Control 39 4.3.2 Main Control 40 4.3.3 DAC Control 41 4.4 Dynamic Element Matching Block 44 4.4.1 Pseudo Random Number Generator 45 4.4.2 Encoder 45 4.5 Post-Layout Simulation 46 4.6 Summary 48 Chapter 5 Experimental Results 49 5.1 Introduction 49 5.2 Print Circuit Board Design 49 5.3 Measurement Setup 50 5.4 Measurement Results 51 5.5 Fault Diagnosis 58 5.6 Summary 64 Chapter 6 Conclusions and Future Works 65 6.1 Conclusions 65 6.2 Future Works 65 Bibliography 678897269 bytesapplication/pdf論文公開時間：2019/03/09論文使用權限：同意有償授權(權利金給回饋學校)類比數位轉換器動態元件匹配連續漸進式thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263873/1/ntu-103-R98943141-1.pdf