Lu, Yu ChengYu ChengLuLee, MingMingLeeHuang, Zi YuanZi YuanHuangVITA PI-HO HU2023-08-212023-08-212023-01-019798350334166https://scholars.lib.ntu.edu.tw/handle/123456789/634617In this work, we analyze the monolithic 3D (M3D) SRAM cells with front-end-of-line (FEOL) Si FinFETs and back-end-of-line (BEOL)-compatible MOS transistors. Two transistor-level partitioning designs for M3D SRAM cells, including (1) 3DPGBEOL: BEOL pass-gate (PG) nFETs with FEOL pull-down (PD) and pull-up (PU) transistors and (2) 3DPUBEOL: BEOL PU pFETs with FEOL PD/PG nFETs, are investigated, respectively. Through the iterative electrical-thermal simulations, we demonstrate the on-current criteria ( Ioncrit}}= IonBEOL/ IonFEOL) defined as the Ion ratio of BEOL transistor to FEOL PD nFET for adequate read and write stability. Higher Ioncrit (89%) for 3DPGBEOL SRAM is essential to mitigate the read and write conflict. Compared to conventional 2D Si FinFET SRAM, the 3DPUBEOL SRAM (a) demonstrates low Ioncrit(=12.4%) (b) reduces the cell area (-20.2%); (c) enhances write stability (+70%); (d) improves read (-15%) and write (-23%) speed.conference paper10.1109/VLSI-TSA/VLSI-DAT57221.2023.101341522-s2.0-85162978536https://api.elsevier.com/content/abstract/scopus_id/85162978536